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Message-ID: <CAFg_LQXmcPZnCUP1eWt-cH2=rHtDRWVWDyg7RXK6_QW=eYnp9g@mail.gmail.com>
Date:   Mon, 21 Aug 2023 17:07:45 +0800
From:   Jinrong Liang <ljr.kernel@...il.com>
To:     Like Xu <like.xu.linux@...il.com>
Cc:     Paolo Bonzini <pbonzini@...hat.com>,
        David Matlack <dmatlack@...gle.com>,
        Aaron Lewis <aaronlewis@...gle.com>,
        Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Jinrong Liang <cloudliang@...cent.com>, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Sean Christopherson <seanjc@...gle.com>,
        Jim Mattson <jmattson@...gle.com>
Subject: Re: [PATCH v3 02/11] KVM: selftests: Add pmu.h for PMU events and
 common masks

Like Xu <like.xu.linux@...il.com> 于2023年8月21日周一 16:56写道:
>
> On 14/8/2023 7:50 pm, Jinrong Liang wrote:
> > +#define ARCH_PERFMON_EVENTSEL_EDGE           BIT_ULL(18)
> > +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL    BIT_ULL(19)
> > +#define ARCH_PERFMON_EVENTSEL_INT            BIT_ULL(20)
> > +#define ARCH_PERFMON_EVENTSEL_ANY            BIT_ULL(21)
> > +#define ARCH_PERFMON_EVENTSEL_ENABLE         BIT_ULL(22)
> > +#define ARCH_PERFMON_EVENTSEL_INV            BIT_ULL(23)
> > +#define ARCH_PERFMON_EVENTSEL_CMASK          GENMASK_ULL(31, 24)
>
> Could you write more test cases to cover all EVENTSEL bits including ENABLE bit ?

I am more than willing to write additional test cases to cover all
EVENTSEL bits, including the ENABLE bit.

If you have any specific suggestions or scenarios you'd like me to
cover in the new test cases, please feel free to share them. I am open
to any ideas that can further improve the coverage and quality of our
selftests.

Thanks

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