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Message-Id: <20230822155333.2261262-6-Frank.Li@nxp.com>
Date:   Tue, 22 Aug 2023 11:53:33 -0400
From:   Frank Li <Frank.Li@....com>
To:     frank.li@....com, shawnguo@...nel.org, joy.zou@....com,
        shenwei.wang@....com, sherry.sun@....com
Cc:     clin@...e.com, conor+dt@...nel.org, devicetree@...r.kernel.org,
        eagle.zhou@....com, festevam@...il.com, imx@...ts.linux.dev,
        kernel@...gutronix.de, krzysztof.kozlowski+dt@...aro.org,
        leoyang.li@....com, linux-arm-kernel@...ts.infradead.org,
        linux-imx@....com, linux-kernel@...r.kernel.org,
        pierre.gondois@....com, robh+dt@...nel.org, s.hauer@...gutronix.de
Subject: [PATCH 5/5] arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3

Enable uart2 and uart5 for imx8qxp-mek board.

Signed-off-by: Frank Li <Frank.Li@....com>
---
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 7924b0969ad8..99611729943c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -187,6 +187,18 @@ &lpuart0 {
 	status = "okay";
 };
 
+&lpuart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart2>;
+	status = "okay";
+};
+
+&lpuart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart3>;
+	status = "okay";
+};
+
 &mu_m0 {
 	status = "okay";
 };
@@ -340,6 +352,20 @@ IMX8QXP_UART0_TX_ADMA_UART0_TX				0x06000020
 		>;
 	};
 
+	pinctrl_lpuart2: lpuart2grp {
+		fsl,pins = <
+			IMX8QXP_UART2_TX_ADMA_UART2_TX          0x06000020
+			IMX8QXP_UART2_RX_ADMA_UART2_RX          0x06000020
+		>;
+	};
+
+	pinctrl_lpuart3: lpuart3grp {
+		fsl,pins = <
+			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX       0x06000020
+			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX       0x06000020
+		>;
+	};
+
 	pinctrl_typec: typecgrp {
 		fsl,pins = <
 			IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03                        0x06000021
-- 
2.34.1

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