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Message-ID: <d93902ee-c305-42cb-9d0d-1f0971ab3a70@quicinc.com>
Date: Tue, 22 Aug 2023 09:57:10 +0530
From: Om Prakash Singh <quic_omprsing@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
<konrad.dybcio@...aro.org>
CC: <agross@...nel.org>, <andersson@...nel.org>, <conor+dt@...nel.org>,
<davem@...emloft.net>, <devicetree@...r.kernel.org>,
<herbert@...dor.apana.org.au>, <krzysztof.kozlowski+dt@...aro.org>,
<linux-arm-msm@...r.kernel.org>, <linux-crypto@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <marijn.suijten@...ainline.org>,
<robh+dt@...nel.org>, <vkoul@...nel.org>
Subject: Re: [PATCH 1/3] dt-bindings: crypto: qcom,prng: Add SM8450
On 8/21/2023 11:37 AM, Krzysztof Kozlowski wrote:
> On 21/08/2023 02:52, Om Prakash Singh wrote:
>> I meant first one. using "qcom,rng-ee".
>
> Then please provide some reasons.
>
New IP block available on SM8450 and newer platform is true random
number generator with it's entropy source. Also it is NIST SP800 90B
compliant.
By introducing "qcom,rng-ee" I am also planning to add hwrng support in
driver.
>>
>> I am looking for generic compatible string for all SoCs for which core
>> clock can be optional, same as we have "qcom,prng-ee".
>
> There is a generic compatible already... but anyway, is the clock really
> optional? Or just configured by firmware?
>
Clock is configured using security firmware.
>>
>> If we are using SoC name in compatible string, for each SoC support we
>> need to update qcom,prng.yaml file.
>
> So you were talking about second case from my email? Still not sure what
> you want to propose, but just in case - please always follow DT bindings
> guidelines:
>
> https://elixir.bootlin.com/linux/v6.1-rc1/source/Documentation/devicetree/bindings/writing-bindings.rst#L42
>
> Best regards,
> Krzysztof
>
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