linux-kernel - Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller

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Message-ID: <CAPqJEFrM51aQrcVgj8RFvai4QPR2+iOC=ueqFpU0oNX+h4aQbg@mail.gmail.com>
Date:   Tue, 5 Sep 2023 23:07:11 +0800
From:   Eric Lin <eric.lin@...ive.com>
To:     Conor Dooley <conor@...nel.org>
Cc:     krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        palmer@...belt.com, paul.walmsley@...ive.com,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        zong.li@...ive.com, greentime.hu@...ive.com,
        vincent.chen@...ive.com
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2
 cache controller

Hi Conor and Krzysztof,

On Fri, Jul 21, 2023 at 1:10 AM Conor Dooley <conor@...nel.org> wrote:
>
> Hey Eric,
>
> On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:
> > This add YAML DT binding documentation for SiFive Private L2
> > cache controller
> >
> > Signed-off-by: Eric Lin <eric.lin@...ive.com>
> > Reviewed-by: Zong Li <zong.li@...ive.com>
> > Reviewed-by: Nick Hu <nick.hu@...ive.com>
> > ---
> >  .../bindings/cache/sifive,pl2cache.yaml       | 62 +++++++++++++++++++
>
> btw, your $subject should be "dt-bindings: cache: ...." rather than
> "riscv: sifive".
>
> >  1 file changed, 62 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > new file mode 100644
> > index 000000000000..ee8356c5eeee
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
> > @@ -0,0 +1,62 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright (C) 2023 SiFive, Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SiFive Private L2 Cache Controller
> > +
> > +maintainers:
> > +  - Greentime Hu  <greentime.hu@...ive.com>
> > +  - Eric Lin  <eric.lin@...ive.com>
>
> There's extra spaces in these lines for some reason.
>
> > +
> > +description:
> > +  The SiFive Private L2 Cache Controller is per core and
> > +  communicates with both the upstream L1 caches and
> > +  downstream L3 cache or memory, enabling a high-performance
> > +  cache subsystem.
> > +
> > +allOf:
> > +  - $ref: /schemas/cache-controller.yaml#
> > +
>
> I'm pretty sure that I pointed out last time around that you need to add
> something like in the ccache driver:
>
> select:
>   properties:
>     compatible:
>       contains:
>         enum:
>           - sifive,ccache0
>           - sifive,fu540-c000-ccache
>           - sifive,fu740-c000-ccache
>
> otherwise this binding will be used for anything containing "cache" in
> the dt-binding.
> For this binding, I think that the following is sufficient:
>
> select:
>   properties:
>     compatible:
>       contains:
>           const: sifive,pl2cache1
>
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: sifive,pl2cache1
> > +      - const: cache
>
> You omitted the pl2cache0 from here, that needs to come back! You'll end
> up with 2 items entries.
> Either way, I can't take this binding without a soc-specific compatible,
> per sifive-blocks-ip-versioning.txt..
>
Sorry for the late reply.
OK, I will wait until the customer's SoC tape-out before upstreaming
the PL2 cache and PMU drivers.
Thank you for your review.

Best regards,
Eric Lin

> Thanks,
> Conor.