linux-kernel - Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller

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Message-ID: <20250321-spinal-endocrine-aabd38734c32@spud>
Date: Fri, 21 Mar 2025 22:38:00 +0000
From: Conor Dooley <conor@...nel.org>
To: Eric Lin <eric.lin@...ive.com>
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
	conor+dt@...nel.org, palmer@...belt.com, paul.walmsley@...ive.com,
	will@...nel.org, mark.rutland@....com, tglx@...utronix.de,
	peterz@...radead.org, devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
	zong.li@...ive.com, greentime.hu@...ive.com,
	vincent.chen@...ive.com, Nick Hu <nick.hu@...ive.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2
 cache controller

On Thu, Jul 20, 2023 at 06:10:51PM +0100, Conor Dooley wrote:
> On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:

> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: sifive,pl2cache1
> > +      - const: cache
> 
> You omitted the pl2cache0 from here, that needs to come back! You'll end
> up with 2 items entries.
> Either way, I can't take this binding without a soc-specific compatible,
> per sifive-blocks-ip-versioning.txt..

On this last point, what Nick Hu has done for the clint2 would be
acceptable, adding a {} entry to disallow the compatible in isolation
without requiring a soc-specific compatible for hardware that does not
yet exist:
https://lore.kernel.org/all/20250321083507.25298-1-nick.hu@sifive.com/

Maybe that'll allow you to submit a v3 of this work?

Cheers,
Conor

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