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Message-Id: <20230907161242.67190-6-ben.dooks@codethink.co.uk>
Date: Thu, 7 Sep 2023 17:12:41 +0100
From: Ben Dooks <ben.dooks@...ethink.co.uk>
To: linux-pwm@...r.kernel.org
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
ben.dooks@...ethink.co.uk, u.kleine-koenig@...gutronix.de,
Thierry Reding <thierry.reding@...il.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Greentime Hu <greentime.hu@...ive.com>,
jarkko.nikula@...ux.intel.com,
William Salmon <william.salmon@...ive.com>,
Jude Onyenegecha <jude.onyenegecha@...ive.com>
Subject: [PATCH v9 5/6] pwm: dwc: round rate divisions up
As suggested, round up the counter variables to ensure we
always produce a longer period calculation.
Reported-by: Uwe Kleine-König <u.kleine-koenig@...gutronix.de>
Signed-off-by: Ben Dooks <ben.dooks@...ethink.co.uk>
---
drivers/pwm/pwm-dwc-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-dwc-core.c b/drivers/pwm/pwm-dwc-core.c
index 3b856685029d..6358e3345210 100644
--- a/drivers/pwm/pwm-dwc-core.c
+++ b/drivers/pwm/pwm-dwc-core.c
@@ -50,13 +50,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc,
* 2^32 periods.
*/
tmp = state->duty_cycle * dwc->clk_rate;
- tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
+ tmp = DIV_ROUND_UP_ULL(tmp, NSEC_PER_SEC);
if (tmp < 1 || tmp > (1ULL << 32))
return -ERANGE;
low = tmp - 1;
tmp = (state->period - state->duty_cycle) * dwc->clk_rate;
- tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
+ tmp = DIV_ROUND_UP_ULL(tmp, NSEC_PER_SEC);
if (tmp < 1 || tmp > (1ULL << 32))
return -ERANGE;
high = tmp - 1;
--
2.40.1
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