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Message-ID: <CAJve8ok03P-t7pTA9mH=5vvkUy4NtxHac_Z_NM88cs55YQZATg@mail.gmail.com>
Date: Thu, 7 Sep 2023 12:20:29 +0800
From: Haibo Xu <xiaobo55x@...il.com>
To: Andrew Jones <ajones@...tanamicro.com>
Cc: Haibo Xu <haibo1.xu@...el.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Paolo Bonzini <pbonzini@...hat.com>,
Shuah Khan <shuah@...nel.org>, Marc Zyngier <maz@...nel.org>,
Oliver Upton <oliver.upton@...ux.dev>,
James Morse <james.morse@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Zenghui Yu <yuzenghui@...wei.com>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Guo Ren <guoren@...nel.org>,
Conor Dooley <conor.dooley@...rochip.com>,
Greentime Hu <greentime.hu@...ive.com>,
wchen <waylingii@...il.com>,
Daniel Henrique Barboza <dbarboza@...tanamicro.com>,
Sean Christopherson <seanjc@...gle.com>,
Ricardo Koller <ricarkol@...gle.com>,
Vishal Annapurve <vannapurve@...gle.com>,
David Matlack <dmatlack@...gle.com>,
Aaron Lewis <aaronlewis@...gle.com>,
Mingwei Zhang <mizhang@...gle.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Ackerley Tng <ackerleytng@...gle.com>,
Vipin Sharma <vipinsh@...gle.com>,
Maxim Levitsky <mlevitsk@...hat.com>,
Peter Gonda <pgonda@...gle.com>,
Philippe Mathieu-Daudé <philmd@...aro.org>,
Thomas Huth <thuth@...hat.com>, Like Xu <likexu@...cent.com>,
David Woodhouse <dwmw@...zon.co.uk>,
Michal Luczaj <mhal@...x.co>,
zhang songyi <zhang.songyi@....com.cn>,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
kvm@...r.kernel.org, linux-kselftest@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, kvmarm@...ts.linux.dev,
kvm-riscv@...ts.infradead.org
Subject: Re: [PATCH v2 8/8] KVM: riscv: selftests: Add sstc timer test
On Mon, Sep 4, 2023 at 10:58 PM Andrew Jones <ajones@...tanamicro.com> wrote:
>
> On Sat, Sep 02, 2023 at 08:59:30PM +0800, Haibo Xu wrote:
> > Add a KVM selftest to validate the Sstc timer functionality.
> > The test was ported from arm64 arch timer test.
> >
> > Signed-off-by: Haibo Xu <haibo1.xu@...el.com>
> > ---
> > diff --git a/tools/testing/selftests/kvm/riscv/arch_timer.c b/tools/testing/selftests/kvm/riscv/arch_timer.c
> > new file mode 100644
> > index 000000000000..c50a33c1e4f9
> > --- /dev/null
> > +++ b/tools/testing/selftests/kvm/riscv/arch_timer.c
> > @@ -0,0 +1,130 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * arch_timer.c - Tests the riscv64 sstc timer IRQ functionality
> > + *
> > + * The test validates the sstc timer IRQs using vstimecmp registers.
> > + * It's ported from the aarch64 arch_timer test.
> > + *
> guest_run[_stage]() can be shared with aarch64, we just have a single
> stage=0 for riscv.
>
Yes, we can. But if we share the guest_run[_stage]() by moving it to
kvm/arch_timer.c
or kvm/include/timer_test.h, we need to declare extra sub-functions
somewhere in a
header file(etc. guest_configure_timer_action()).
> > +
> > +static void guest_code(void)
> > +{
> > + uint32_t cpu = guest_get_vcpuid();
> > + struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
> > +
> > + local_irq_disable();
> > + timer_irq_disable();
> > + local_irq_enable();
>
> I don't think we need to disable all interrupts when disabling the timer
> interrupt.
>
There is no local_irq_disable() protection during the initial debug
phase, but the test always
fail with below error messages:
Guest assert failed, vcpu 0; stage; 0; iter: 0
==== Test Assertion Failure ====
riscv/arch_timer.c:78: config_iter + 1 == irq_iter
pid=585 tid=586 errno=4 - Interrupted system call
(stack trace empty)
0x1 != 0x0 (config_iter + 1 != irq_iter)
To be frank, I am not quite sure why the local_irq_disable/enable() matters.
One possible reason may be some timer irq was triggered before we set up the
timecmp register.
> > +
> > + guest_run(shared_data);
> > +
> > + GUEST_DONE();
> > +}
> > +
> > +void test_vm_cleanup(struct kvm_vm *vm)
> > +{
> > + kvm_vm_free(vm);
> > +}
> > --
> > 2.34.1
> >
>
> Thanks,
> drew
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