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Message-ID: <CAA8EJppXxiX7+6nhfKyJYDU0i2pkBzXL5J3EQUapLJXxx3b=HA@mail.gmail.com>
Date: Thu, 7 Sep 2023 16:54:56 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Varadarajan Narayanan <quic_varada@...cinc.com>
Cc: ilia.lin@...nel.org, agross@...nel.org, andersson@...nel.org,
konrad.dybcio@...aro.org, rafael@...nel.org,
viresh.kumar@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
mturquette@...libre.com, sboyd@...nel.org,
quic_kathirav@...cinc.com, linux-pm@...r.kernel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v1 04/10] clk: qcom: apss-ipq6018: ipq5332: add safe
source switch for a53pll
On Thu, 7 Sept 2023 at 08:22, Varadarajan Narayanan
<quic_varada@...cinc.com> wrote:
>
> Stromer Plus PLL found on IPQ53xx doesn't support dynamic
> frequency scaling. To achieve the same, we need to park the APPS
> PLL source to GPLL0, re configure the PLL and then switch the
> source to APSS_PLL_EARLY.
>
> To support this, register a clock notifier to get the PRE_RATE
> and POST_RATE notification. Change the APSS PLL source to GPLL0
> when PRE_RATE notification is received, then configure the PLL
> and then change back the source to APSS_PLL_EARLY.
This means that we are changing the parents behind the back of CCF,
which is not great.
>
> Signed-off-by: Kathiravan T <quic_kathirav@...cinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> ---
> drivers/clk/qcom/apss-ipq6018.c | 54 ++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
> index 4e13a08..ffb6ab5 100644
> --- a/drivers/clk/qcom/apss-ipq6018.c
> +++ b/drivers/clk/qcom/apss-ipq6018.c
> @@ -9,8 +9,11 @@
> #include <linux/clk-provider.h>
> #include <linux/regmap.h>
> #include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/soc/qcom/smem.h>
>
> #include <dt-bindings/clock/qcom,apss-ipq.h>
> +#include <dt-bindings/arm/qcom,ids.h>
>
> #include "common.h"
> #include "clk-regmap.h"
> @@ -84,15 +87,64 @@ static const struct qcom_cc_desc apss_ipq6018_desc = {
> .num_clks = ARRAY_SIZE(apss_ipq6018_clks),
> };
>
> +static int cpu_clk_notifier_fn(struct notifier_block *nb, unsigned long action,
> + void *data)
> +{
> + u8 index;
> + int err;
> +
> + if (action == PRE_RATE_CHANGE)
> + index = P_GPLL0;
I don't see P_GPLL0 being supported in the ipq6018 driver.
> + else if (action == POST_RATE_CHANGE)
> + index = P_APSS_PLL_EARLY;
You also have to handle ABORT_RATE_CHANGE here.
> + else
> + return 0;
> +
> + err = clk_rcg2_mux_closest_ops.set_parent(&apcs_alias0_clk_src.clkr.hw,
> + index);
> +
> + return notifier_from_errno(err);
> +}
> +
> +static struct notifier_block cpu_clk_notifier = {
> + .notifier_call = cpu_clk_notifier_fn,
> +};
> +
> static int apss_ipq6018_probe(struct platform_device *pdev)
> {
> struct regmap *regmap;
> + u32 soc_id;
> + int ret;
> +
> + ret = qcom_smem_get_soc_id(&soc_id);
> + if (ret)
> + return ret;
>
> regmap = dev_get_regmap(pdev->dev.parent, NULL);
> if (!regmap)
> return -ENODEV;
>
> - return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
> + ret = qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
> + if (ret)
> + return ret;
> +
> + switch (soc_id) {
> + /*
> + * Only below variants of IPQ53xx support scaling
> + */
> + case QCOM_ID_IPQ5332:
> + case QCOM_ID_IPQ5322:
> + case QCOM_ID_IPQ5300:
Please use compat strings instead of using the soc-id.
> + ret = clk_notifier_register(apcs_alias0_clk_src.clkr.hw.clk,
> + &cpu_clk_notifier);
> + if (ret)
> + return ret;
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> }
>
> static struct platform_driver apss_ipq6018_driver = {
> --
> 2.7.4
>
--
With best wishes
Dmitry
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