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Message-ID: <a9c3d43a-af26-44a0-9352-4666107f9f56@sirena.org.uk>
Date:   Thu, 7 Sep 2023 15:21:04 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Joerg Schambacher <joerg.hifiberry@...il.com>
Cc:     a-krasser@...com, joerg@...iberry.com,
        Liam Girdwood <lgirdwood@...il.com>,
        Jaroslav Kysela <perex@...ex.cz>,
        Takashi Iwai <tiwai@...e.com>,
        Uwe Kleine-König 
        <u.kleine-koenig@...gutronix.de>,
        Zhang Qilong <zhangqilong3@...wei.com>,
        alsa-devel@...a-project.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] ASoC: Adds support for TAS575x to the pcm512x driver

On Thu, Sep 07, 2023 at 06:12:05PM +0200, Joerg Schambacher wrote:

> +		if (pcm512x->tas_device) {
> +			/* set necessary PLL coeffs for amp
> +			 * according to spec only 2x and 4x MCLKs
> +			 * possible
> +			 */
> +			ret = regmap_write(pcm512x->regmap,
> +					   PCM512x_PLL_COEFF_0, 0x01);
> +			if (mck_rate > 25000000UL)
> +				ret = regmap_write(pcm512x->regmap,
> +						   PCM512x_PLL_COEFF_1, 0x02);
> +			else
> +				ret = regmap_write(pcm512x->regmap,
> +						   PCM512x_PLL_COEFF_1, 0x04);

I would name this quirk something a bit more specific - it seems likely
that there might be future TASxxxx devices which need different quirks.
If it's a limited range of MCLK multipliers perhaps something about how
the PLL is limited, or just make the quirk data being to specify min/max
for the multiplier?

> +		if (!pcm512x->tas_device) {
> +			ret = regmap_update_bits(pcm512x->regmap,
> +						 PCM512x_PLL_EN, PCM512x_PLLE, 0);
> +		} else {
> +			/* leave PLL enabled for amp clocking */
> +			ret = regmap_write(pcm512x->regmap,
> +					   PCM512x_PLL_EN, 0x01);
> +			dev_dbg(component->dev, "Enabling PLL for TAS575x\n");
> +		}

This is probably a separate quirk?  I'm a bit concerned about what's
turning the PLL off here...

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