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Message-ID: <87ttrwap4s.fsf@all.your.base.are.belong.to.us>
Date: Thu, 14 Sep 2023 14:57:39 +0200
From: Björn Töpel <bjorn@...nel.org>
To: Conor Dooley <conor.dooley@...rochip.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
linux-riscv@...ts.infradead.org, Andy Chiu <andy.chiu@...ive.com>,
Greentime Hu <greentime.hu@...ive.com>,
"Jason A . Donenfeld" <Jason@...c4.com>,
Samuel Neves <sneves@....uc.pt>,
Björn Töpel
<bjorn@...osinc.com>, Heiko Stuebner <heiko@...ech.de>,
Herbert Xu <herbert@...dor.apana.org.au>,
"David S. Miller" <davem@...emloft.net>,
linux-crypto@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH 6/6] riscv: Add BLAKE2s V implementation
Conor Dooley <conor.dooley@...rochip.com> writes:
> On Tue, Sep 12, 2023 at 01:57:28PM +0200, Björn Töpel wrote:
>> From: Björn Töpel <bjorn@...osinc.com>
>>
>> BLAKE2s is used in various places, most notably in Wireguard, and as
>> of v5.17 in drivers/char/random.
>>
>> Add a BLAKE2s implementation using the V-extension. This is a
>> translation of the x86-64 AVX512 variant
>> (arch/x86/crypto/blake2s-core.S) to the RISC-V V-extension.
>>
>> The AVX512 variant requires registers >= 256b (ymm*), and hence this
>> implementation requires a VLEN of >=256.
>>
>> The implementation passes the kernel BLAKE2s selftest, and has been
>> tested on spike and qemu.
>>
>> Instruction-wise, the V-variant uses 60% less instructions than the
>> generic, C-based, implementation.
>>
>> Signed-off-by: Björn Töpel <bjorn@...osinc.com>
>
>> arch/riscv/crypto/blake2s-v.S | 164 +++++++++++++++++++++++++++++++
>
>
> This file is currently being built for !RISCV_ISA_V, leading to build errors
> for obvious reasons. Eg:
> ../arch/riscv/crypto/blake2s-v.S:62:2: error: instruction requires the
> following: 'V' (Vector Extension for Application Processors), 'Zve32x'
> or 'Zve64x' (Vector Extensions for Embedded Processors)
Thanks, noted for the next rev!
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