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Message-Id: <20230917170546.2097352-1-sharath.kumar.d.m@intel.com>
Date:   Sun, 17 Sep 2023 22:35:44 +0530
From:   sharath.kumar.d.m@...el.com
To:     helgaas@...nel.org
Cc:     bhelgaas@...gle.com, dinguyen@...nel.org, kw@...ux.com,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        lpieralisi@...nel.org, robh@...nel.org, sharath.kumar.d.m@...el.com
Subject: [PATCH v4 0/2] PCI: altera: add support to agilex family

From: D M Sharath Kumar <sharath.kumar.d.m@...el.com>

added new callback for
1) read,write to root port configuration registers
2) read,write to endpoint configuration registers
3) root port interrupt handler

agilex and newer platforms need to implemant the callback and generic root
port driver should work ( without much changes ) , legacy platforms (arria
 and startix) implement configuration read,write directly in wrapper
api _altera_pcie_cfg_read/_altera_pcie_cfg_write

changelog v2:
saperated into two patches
1.refactored the driver for easily portability to future Altera FPGA
platforms
2.added support for "Agilex" FPGA

this driver supports PCI RP IP on Agilex FPGA, as these are FPGA its up
to the user to add PCI RP or not ( as per his needs). we are not adding
the device tree as part of this commit. we are expecting the add device
tree changes only if he is adding PCI RP IP in his design

changelog v3:
incorporate review comments from Bjorn Helgaas

changelog v4:
added below callback for root bus
alt_read/write_own_cfg
added below callback for non-root buses
alt_read/write_other_cfg

D M Sharath Kumar (2):
  PCI: altera: refactor driver for supporting new platform
  PCI: altera: add support for agilex family fpga

 drivers/pci/controller/pcie-altera.c | 313 ++++++++++++++++++++++++---
 1 file changed, 280 insertions(+), 33 deletions(-)

-- 
2.34.1

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