[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZQh1p5umcz7V4jXG@intel.com>
Date: Mon, 18 Sep 2023 12:07:03 -0400
From: Rodrigo Vivi <rodrigo.vivi@...el.com>
To: Alexander Usyskin <alexander.usyskin@...el.com>
CC: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Lucas De Marchi <lucas.demarchi@...el.com>,
Daniele Ceraolo Spurio <daniele.ceraolospurio@...el.com>,
<linux-kernel@...r.kernel.org>,
"Tomas Winkler" <tomas.winkler@...el.com>,
<intel-xe@...ts.freedesktop.org>
Subject: Re: [Intel-xe] [PATCH v2 1/4] drm/xe/gsc: add HECI2 register offsets
On Thu, Sep 14, 2023 at 11:01:35AM +0300, Alexander Usyskin wrote:
> From: Vitaly Lubart <vitaly.lubart@...el.com>
>
> Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@...el.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@...el.com>
> ---
> drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 39d7b0740bf0..4cbc3062cb9a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -33,6 +33,10 @@
> #define XEHPC_BCS6_RING_BASE 0x3ea000
> #define XEHPC_BCS7_RING_BASE 0x3ec000
> #define XEHPC_BCS8_RING_BASE 0x3ee000
> +
> +#define DG1_GSC_HECI2_BASE 0x00259000
> +#define DG2_GSC_HECI2_BASE 0x00374000
matches the i915 ones, so
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@...el.com>
> +
> #define GSCCS_RING_BASE 0x11a000
> #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
> #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)
> --
> 2.34.1
>
Powered by blists - more mailing lists