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Message-ID: <CAJM55Z-huG6KSLywzA0Zih=MtzqvL0w+CxrqN7CKUrzor_A65g@mail.gmail.com>
Date: Fri, 22 Sep 2023 11:36:07 -0500
From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
To: William Qiu <william.qiu@...rfivetech.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-mmc@...r.kernel.org
Cc: Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Jaehoon Chung <jh80.chung@...sung.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Subject: Re: [PATCH v3 3/3] riscv: dts: starfive: add assigned-clock* to limit frquency
William Qiu wrote:
> In JH7110 SoC, we need to go by-pass mode, so we need add the
> assigned-clock* properties to limit clock frquency.
>
> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
Thanks!
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
> ---
> .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index d79f94432b27..d1f2ec308bca 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -205,6 +205,8 @@ &i2c6 {
>
> &mmc0 {
> max-frequency = <100000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> + assigned-clock-rates = <50000000>;
> bus-width = <8>;
> cap-mmc-highspeed;
> mmc-ddr-1_8v;
> @@ -221,6 +223,8 @@ &mmc0 {
>
> &mmc1 {
> max-frequency = <100000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> + assigned-clock-rates = <50000000>;
> bus-width = <4>;
> no-sdio;
> no-mmc;
> --
> 2.34.1
>
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