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Message-ID: <f3eba136-74d4-4f54-b35d-ce3236db9f67@quicinc.com>
Date: Wed, 27 Sep 2023 17:42:25 +0530
From: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
"Sricharan Ramabadhran" <quic_srichara@...cinc.com>,
Gokul Sriram Palanisamy <quic_gokulsri@...cinc.com>,
Varadarajan Narayanan <quic_varada@...cinc.com>,
Anusha Rao <quic_anusha@...cinc.com>,
Devi Priya <quic_devipriy@...cinc.com>,
Jassi Brar <jassisinghbrar@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 08/11] arm64: dts: qcom: ipq8074: include the GPLL0 as
clock provider for mailbox
On 9/27/2023 5:03 PM, Konrad Dybcio wrote:
> On 14.09.2023 08:59, Kathiravan Thirumoorthy wrote:
>> While the kernel is booting up, APSS PLL will be running at 800MHz with
>> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
>> configured to the rate based on the opp table and the source also will
>> be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
>> with this inclusion, CPU Freq correctly reports that CPU is running at
>> 800MHz rather than 24MHz.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
>> ---
> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
>
> Konrad
Thanks Konrad.
I just realized that, in commit message, the statement "APSS PLL will be
running at 800MHz" should be "APSS clock / CPU clock will be running at
800MHz".
Bjorn, will you be able to fix it up while applying (all 4 DTS changes
needs update) or shall I respin it?
Thanks,
Kathiravan T.
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