lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230928105137.5ljhuoxjc7et5thw@dhruva>
Date:   Thu, 28 Sep 2023 16:21:37 +0530
From:   Dhruva Gole <d-gole@...com>
To:     Muhammed Efe Cetin <efectn@...l.net>
CC:     <linux-rockchip@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <heiko@...ech.de>, <sebastian.reichel@...labora.com>,
        <jonas@...boo.se>, <megi@....cz>
Subject: Re: [PATCH v3 3/3] arm64: dts: rockchip: Add Orange Pi 5

Hi,

On Aug 21, 2023 at 18:47:59 +0300, Muhammed Efe Cetin wrote:
> Add initial support for OPi5 that includes support for USB2, PCIe2, Sata,
> Sdmmc, SPI Flash, PMIC.
> 
> Signed-off-by: Muhammed Efe Cetin <efectn@...l.net>
> Reviewed-by: Ondřej Jirman <megi@....cz>
> ---
>  arch/arm64/boot/dts/rockchip/Makefile         |   1 +
>  .../boot/dts/rockchip/rk3588s-orangepi-5.dts  | 673 ++++++++++++++++++
>  2 files changed, 674 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
> 
...

Can you provide some sort of documentation on how I can build and boot
the kernel on this board? I was unable to use the upstream arm64
defconfig with this exact series applied to boot the board.

> +
> +&i2c6 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c6m3_xfer>;
> +	status = "okay";
> +
> +	hym8563: rtc@51 {
> +		compatible = "haoyu,hym8563";
> +		reg = <0x51>;
> +		#clock-cells = <0>;
> +		clock-output-names = "hym8563";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&hym8563_int>;
> +		interrupt-parent = <&gpio0>;
> +		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
> +		wakeup-source;

Are you able to actually use rtc as a wakeup source? I tried this
on a downstream kernel that I mention below..

rtcwake -s 10 -m mem

didn't actually seem to wake the device from deepsleep after 10 seconds.
Do you know what other pins I can use as wakeup sources?

> +	};
> +};
> +
> +&mdio1 {
> +	rgmii_phy1: ethernet-phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";

Just wondering, can you please give some logs of the board with eth
working? The image that I have from opi seems to fail eth? As in I am
not able to see any ip address. here are the logs:

https://gist.github.com/DhruvaG2000/eda2762e35013c8d5ac9f37e818103a3

...

-- 
Best regards,
Dhruva Gole <d-gole@...com>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ