linux-kernel - Re: [PATCH v3 4/4] Documentation/x86: Document resctrl's new sparse

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Message-ID: <b94b695f-f644-4936-60db-b1312fb13667@linux.intel.com>
Date:   Fri, 29 Sep 2023 17:56:33 +0300 (EEST)
From:   Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To:     Maciej Wieczor-Retman <maciej.wieczor-retman@...el.com>
cc:     Fenghua Yu <fenghua.yu@...el.com>,
        Reinette Chatre <reinette.chatre@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
        "H. Peter Anvin" <hpa@...or.com>, Jonathan Corbet <corbet@....net>,
        Peter Newman <peternewman@...gle.com>,
        LKML <linux-kernel@...r.kernel.org>, linux-doc@...r.kernel.org
Subject: Re: [PATCH v3 4/4] Documentation/x86: Document resctrl's new
 sparse_masks

On Fri, 29 Sep 2023, Maciej Wieczor-Retman wrote:

> From: Fenghua Yu <fenghua.yu@...el.com>
> 
> The documentation mentions that non-contiguous bit masks are not
> supported in Intel Cache Allocation Technology (CAT).
> 
> Update the documentation on how to determine if sparse bit masks are
> allowed in L2 and L3 CAT.
> 
> Mention the file with feature support information is located in
> the /sys/fs/resctrl/info/{resource}/ directories and enumerate what
> are the possible outputs on file read operation.
> 
> Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
> Reviewed-by: Peter Newman <peternewman@...gle.com>
> Tested-by: Peter Newman <peternewman@...gle.com>
> Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@...el.com>
> ---
> Changelog v3:
> - Added Peter's tested-by and reviewed-by tags.
> 
> Changelog v2:
> - Change bitmap naming convention to bit mask. (Reinette)
> 
>  Documentation/arch/x86/resctrl.rst | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst
> index cb05d90111b4..4c6421e2aa31 100644
> --- a/Documentation/arch/x86/resctrl.rst
> +++ b/Documentation/arch/x86/resctrl.rst
> @@ -124,6 +124,13 @@ related to allocation:
>  			"P":
>  			      Corresponding region is pseudo-locked. No
>  			      sharing allowed.
> +"sparse_masks":
> +		Indicates if non-contiguous 1s value in CBM is supported.
> +
> +			"0":
> +			      Only contiguous 1s value in CBM is supported.
> +			"1":
> +			      Non-contiguous 1s value in CBM is supported.
>  
>  Memory bandwidth(MB) subdirectory contains the following files
>  with respect to allocation:
> @@ -445,12 +452,13 @@ For cache resources we describe the portion of the cache that is available
>  for allocation using a bitmask. The maximum value of the mask is defined
>  by each cpu model (and may be different for different cache levels). It
>  is found using CPUID, but is also provided in the "info" directory of
> -the resctrl file system in "info/{resource}/cbm_mask". Intel hardware
> +the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware
>  requires that these masks have all the '1' bits in a contiguous block. So
>  0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9
> -and 0xA are not.  On a system with a 20-bit mask each bit represents 5%
> -of the capacity of the cache. You could partition the cache into four
> -equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.
> +and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks
> +if non-contiguous 1s value is supported. On a system with a 20-bit mask
> +each bit represents 5% of the capacity of the cache. You could partition
> +the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000.

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>

-- 
 i.