linux-kernel - Re: [patch V4 14/30] x86/microcode/amd: Read revision from hardware in collect_cpu_info

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 4 Oct 2023 10:32:35 +0200
From:   Borislav Petkov <bp@...en8.de>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     LKML <linux-kernel@...r.kernel.org>, x86@...nel.org,
        "Chang S. Bae" <chang.seok.bae@...el.com>,
        Arjan van de Ven <arjan@...ux.intel.com>,
        Nikolay Borisov <nik.borisov@...e.com>
Subject: Re: [patch V4 14/30] x86/microcode/amd: Read revision from hardware
 in collect_cpu_info_amd()

On Mon, Oct 02, 2023 at 01:59:51PM +0200, Thomas Gleixner wrote:
> Prepare to decrapify the core initialization logic which invokes
> microcode_ops::apply_microcode() several times just to set
> cpu_data::microcode.
> 
> Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
> ---
> V2: New patch
> ---
>  arch/x86/kernel/cpu/microcode/amd.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> --- a/arch/x86/kernel/cpu/microcode/amd.c
> +++ b/arch/x86/kernel/cpu/microcode/amd.c
> @@ -634,12 +634,12 @@ void reload_ucode_amd(unsigned int cpu)
>  
>  static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
>  {
> -	struct cpuinfo_x86 *c = &cpu_data(cpu);
>  	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
> +	u32 dummy __always_unused;
>  	struct ucode_patch *p;
>  
>  	csig->sig = cpuid_eax(0x00000001);
> -	csig->rev = c->microcode;
> +	rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy);
>  
>  	/*
> * a patch could have been loaded early, set uci->mc so that

Skipping that one as the rev needs to be read on the respective CPU for
mixed silicon steppings on AMD.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette