linux-kernel - Re: [PATCH 02/13] arm64: dts: imx8mp: re-parent IMX8MP_CLK_MEDIA_MIPI_PHY1

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Message-Id: <20231004083639.2895890-1-bbara93@gmail.com>
Date:   Wed,  4 Oct 2023 10:36:39 +0200
From:   Benjamin Bara <bbara93@...il.com>
To:     aford173@...il.com
Cc:     abelvesa@...nel.org, bbara93@...il.com, benjamin.bara@...data.com,
        conor+dt@...nel.org, devicetree@...r.kernel.org,
        festevam@...il.com, frank@...manns.dev, kernel@...gutronix.de,
        krzysztof.kozlowski+dt@...aro.org,
        linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
        linux-imx@....com, linux-kernel@...r.kernel.org,
        linux@...linux.org.uk, mripard@...nel.org, mturquette@...libre.com,
        peng.fan@....com, robh+dt@...nel.org, s.hauer@...gutronix.de,
        sboyd@...nel.org, shawnguo@...nel.org
Subject: Re: [PATCH 02/13] arm64: dts: imx8mp: re-parent IMX8MP_CLK_MEDIA_MIPI_PHY1_REF

Hi Adam,

thanks for the feedback!

On Tue, 3 Oct 2023 at 15:02, Adam Ford <aford173@...il.com> wrote:
> From what I can see, it looks like the IMX8MP_CLK_MEDIA_MIPI_PHY1_REF
> parent is being set to IMX8MP_CLK_24M.  Isn't that the default? I also
> don't think we need to set a 24MHz clock to 24MHz if that's the
> default.

I can retry (have the patch applied since then), but as far as I
remember, it was not. What was even funnier was that media_mipi_phy1_ref
hat a divider != 1 set (it is a composite), so it wasn't sufficient to
just re-parent it to OSC_24M - probably because set_rate() was called
before it was re-parented to OSC_24M. But thanks for the catch, I will
take a look again and adapt it if possible.

Regards
Benjamin

> If that is the case, I would suggest we try to remove the assignment
> altogether to make the device tree simpler and less to untangle if a
> board needs to manually manipulate the clocks for some specific
> reason.
>
> adam
>
> >
> > Cc: Adam Ford <aford173@...il.com>
> > Signed-off-by: Benjamin Bara <benjamin.bara@...data.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 14 ++++++--------
> >  1 file changed, 6 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index c946749a3d73..9539d747e28e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -1640,11 +1640,6 @@ mipi_dsi: dsi@...60000 {
> >                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
> >                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
> >                                 clock-names = "bus_clk", "sclk_mipi";
> > -                               assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
> > -                                                 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
> > -                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> > -                                                        <&clk IMX8MP_CLK_24M>;
> > -                               assigned-clock-rates = <200000000>, <24000000>;
> >                                 samsung,pll-clock-frequency = <24000000>;
> >                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> >                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
> > @@ -1747,13 +1742,16 @@ media_blk_ctrl: blk-ctrl@...c0000 {
> >                                                   <&clk IMX8MP_CLK_MEDIA_APB>,
> >                                                   <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
> >                                                   <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
> > -                                                 <&clk IMX8MP_VIDEO_PLL1>;
> > +                                                 <&clk IMX8MP_VIDEO_PLL1>,
> > +                                                 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
> >                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
> >                                                          <&clk IMX8MP_SYS_PLL1_800M>,
> >                                                          <&clk IMX8MP_VIDEO_PLL1_OUT>,
> > -                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>;
> > +                                                        <&clk IMX8MP_VIDEO_PLL1_OUT>,
> > +                                                        <&clk IMX8MP_CLK_24M>;
> >                                 assigned-clock-rates = <500000000>, <200000000>,
> > -                                                      <0>, <0>, <1039500000>;
> > +                                                      <0>, <0>, <1039500000>,
> > +                                                      <24000000>;
> >                                 #power-domain-cells = <1>;
> >
> >                                 lvds_bridge: bridge@5c {
> >
> > --
> > 2.34.1
> >