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Message-Id: <20231012-pointless-underpaid-649da93b1762@spud>
Date: Thu, 12 Oct 2023 10:24:18 +0100
From: Conor Dooley <conor@...nel.org>
To: kernel@...il.dk, conor@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, paul.walmsley@...ive.com,
palmer@...belt.com, aou@...s.berkeley.edu,
william.qiu@...rfivetech.com, linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Nam Cao <namcao@...utronix.de>
Cc: Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v2] riscv: dts: starfive: visionfive 2: correct spi's ss pin
From: Conor Dooley <conor.dooley@...rochip.com>
On Thu, 12 Oct 2023 11:17:29 +0200, Nam Cao wrote:
> The ss pin of spi0 is the same as sck pin. According to the
> visionfive 2 documentation, it should be pin 49 instead of 48.
>
>
Applied to riscv-dt-fixes, thanks!
[1/1] riscv: dts: starfive: visionfive 2: correct spi's ss pin
https://git.kernel.org/conor/c/cf98fe6b579e
Thanks,
Conor.
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