lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <a007c3a9-0a68-4f4c-bcea-4ffc111939a1@tuxon.dev>
Date:   Fri, 13 Oct 2023 08:45:52 +0300
From:   claudiu beznea <claudiu.beznea@...on.dev>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     magnus.damm@...il.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        mturquette@...libre.com, sboyd@...nel.org,
        linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
        Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH 4/6] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2

Hi, Geert,

Thanks for reviewing!

On 12.10.2023 17:36, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> Thanks for your patch!
> 
> On Tue, Oct 10, 2023 at 3:27 PM Claudiu <claudiu.beznea@...on.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>>
>> Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI3,
> 
> SSI0
> 
>> IRQ0. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0 is done with a switch
> 
> and IRQ1 (twice). Or just say "The selection is done ...".
> 
>> button. To be able to select b/w these a compilation flag has been added
>> (SW_SD2_EN) at the moment being instantiated to select SDHI2.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> 
>> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
>> @@ -13,14 +13,21 @@
>>   * @SW_SD0_DEV_SEL:
>>   *     0 - SD0 is connected to eMMC
>>   *     1 - SD0 is connected to uSD0 card
>> + * @SW_SD2_EN:
>> + *     0 - SCIF1, SSI3, IRQ0, IRQ1 connected to SoC
> 
> SSI0
> 
>> + *     1 - SD2 is connected to SoC
>>   */
>>  #define SW_SD0_DEV_SEL 1
>> +#define SW_SD2_EN      1
> 
>> @@ -100,6 +125,19 @@ &sdhi0 {
>>  };
>>  #endif
>>
>> +#if SW_SD2_EN
>> +&sdhi2 {
>> +       pinctrl-0 = <&sdhi2_pins>;
>> +       pinctrl-1 = <&sdhi2_pins>;
>> +       pinctrl-names = "default", "state_uhs";
> 
> Do you need two states if there is only a single voltage?
> AFAIK, UHS needs 1.8V.

I had the impression that driver needs them both anyway. I double checked
now and it seems it is not the case. I'll update it in the next version.

Thank you,
Claudiu Beznea

> 
>> +       vmmc-supply = <&vcc_sdhi2>;
>> +       vqmmc-supply = <&reg_3p3v>;
>> +       bus-width = <4>;
>> +       max-frequency = <50000000>;
>> +       status = "okay";
>> +};
>> +#endif
>> +
>>  &pinctrl {
>>         sdhi0_pins: sd0 {
>>                 data {
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ