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Message-ID: <9a482d0b-e2f3-116a-1feb-d0b49bc21554@intel.com>
Date: Fri, 13 Oct 2023 20:56:52 +0800
From: Yi Liu <yi.l.liu@...el.com>
To: "Tian, Kevin" <kevin.tian@...el.com>,
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Subject: Re: [PATCH v5 09/11] iommu/vt-d: Add iotlb flush for nested domain
On 2023/9/27 14:53, Tian, Kevin wrote:
>> From: Liu, Yi L <yi.l.liu@...el.com>
>> Sent: Thursday, September 21, 2023 3:54 PM
>> +
>> + /* REVISIT:
>> + * VT-d has defined ITE, ICE, IQE for invalidation failure per hardware,
>> + * but no error code yet, so just set the error code to be 0.
>> + */
>> + *cerror_idx = 0;
>> +
>
> Is it "hardware doesn't provide error code now though it's defined in
> spec" or "intel-iommu driver doesn't retrieve the error code though
> it's provided by the hardware"?
I didn't see vtd spec defines error code for cache invalidation. :(
>
> Is there guarantee that '0' isn't used for an existing error code or
> won't be used for any new error code later?
may need to check it.
--
Regards,
Yi Liu
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