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Message-ID: <04645ece5398efdf03e8ab4bb874a0ba.sboyd@kernel.org>
Date: Wed, 18 Oct 2023 16:58:47 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Varadarajan Narayanan <quic_varada@...cinc.com>, agross@...nel.org,
andersson@...nel.org, conor+dt@...nel.org,
devicetree@...r.kernel.org, ilia.lin@...nel.org,
konrad.dybcio@...aro.org, krzysztof.kozlowski+dt@...aro.org,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
mturquette@...libre.com, quic_kathirav@...cinc.com,
rafael@...nel.org, robh+dt@...nel.org, viresh.kumar@...aro.org
Cc: Varadarajan Narayanan <quic_varada@...cinc.com>
Subject: Re: [PATCH v3 1/8] clk: qcom: clk-alpha-pll: introduce stromer plus ops
Quoting Varadarajan Narayanan (2023-10-18 02:29:14)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 4edbf77..f839a31 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -2508,3 +2508,60 @@ const struct clk_ops clk_alpha_pll_stromer_ops = {
> .set_rate = clk_alpha_pll_stromer_set_rate,
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
> +
> +static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long prate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + u32 l, alpha_width = pll_alpha_width(pll);
> + int ret;
> + u64 a;
> +
> + rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
> +
> + regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
It still assumes the clk is always enabled. Please read back the
register value and make sure the PLL was already enabled before
restoring the enable state of the clk.
> +
> + /* Delay of 2 output clock ticks required until output is disabled */
> + udelay(1);
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