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Message-ID: <20231019135810.3657665-1-peterlin@andestech.com>
Date: Thu, 19 Oct 2023 21:58:10 +0800
From: Yu Chien Peter Lin <peterlin@...estech.com>
To: <geert+renesas@...der.be>, <magnus.damm@...il.com>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <paul.walmsley@...ive.com>,
<palmer@...belt.com>, <aou@...s.berkeley.edu>,
<linux-renesas-soc@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
CC: <prabhakar.mahadev-lad.rj@...renesas.com>, <tim609@...estech.com>,
<dylan@...estech.com>, <locus84@...estech.com>,
<dminus@...estech.com>,
"Yu Chien Peter Lin" <peterlin@...estech.com>
Subject: [PATCH v2 04/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
The Andes INTC allows AX45MP cores to handle custom local
interrupts, such as the performance monitor overflow interrupt.
Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
---
Changes v1 -> v2:
- New patch
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 8a726407fb76..a6345469e8c9 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -37,7 +37,7 @@ cpu0: cpu@0 {
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
+ compatible = "andestech,cpu-intc";
interrupt-controller;
};
};
--
2.34.1
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