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Message-ID: <CAMuHMdX+8RUpmhbcBjohZ5oF+wtakfNpwrxGFbZJvTN8_aJv9g@mail.gmail.com>
Date: Fri, 20 Oct 2023 09:26:31 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Yu Chien Peter Lin <peterlin@...estech.com>
Cc: geert+renesas@...der.be, magnus.damm@...il.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, linux-renesas-soc@...r.kernel.org,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
prabhakar.mahadev-lad.rj@...renesas.com, tim609@...estech.com,
dylan@...estech.com, locus84@...estech.com, dminus@...estech.com
Subject: Re: [PATCH v2 04/10] riscv: dts: renesas: r9a07g043f: Update
compatible string to use Andes INTC
Hi Yu,
On Thu, Oct 19, 2023 at 4:01 PM Yu Chien Peter Lin
<peterlin@...estech.com> wrote:
> The Andes INTC allows AX45MP cores to handle custom local
> interrupts, such as the performance monitor overflow interrupt.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> ---
> Changes v1 -> v2:
> - New patch
Thanks for your patch!
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -37,7 +37,7 @@ cpu0: cpu@0 {
>
> cpu0_intc: interrupt-controller {
> #interrupt-cells = <1>;
> - compatible = "riscv,cpu-intc";
> + compatible = "andestech,cpu-intc";
This compatible value is not documented. Perhaps it was introduced
in an earlier patch in the series, to which I was not CCed?
Threading is broken, so I can't easily find the whole series in lore:
https://lore.kernel.org/all/20231019135810.3657665-1-peterlin@andestech.com/
> interrupt-controller;
> };
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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