linux-kernel - [PATCH v3 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string

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Message-ID: <20231022151858.2479969-5-peterlin@andestech.com>
Date:   Sun, 22 Oct 2023 23:18:49 +0800
From:   Yu Chien Peter Lin <peterlin@...estech.com>
To:     <acme@...nel.org>, <adrian.hunter@...el.com>,
        <ajones@...tanamicro.com>, <alexander.shishkin@...ux.intel.com>,
        <andre.przywara@....com>, <anup@...infault.org>,
        <aou@...s.berkeley.edu>, <atishp@...shpatra.org>,
        <conor+dt@...nel.org>, <conor.dooley@...rochip.com>,
        <conor@...nel.org>, <devicetree@...r.kernel.org>,
        <dminus@...estech.com>, <evan@...osinc.com>,
        <geert+renesas@...der.be>, <guoren@...nel.org>, <heiko@...ech.de>,
        <irogers@...gle.com>, <jernej.skrabec@...il.com>,
        <jolsa@...nel.org>, <jszhang@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>,
        <linux-renesas-soc@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>, <linux-sunxi@...ts.linux.dev>,
        <locus84@...estech.com>, <magnus.damm@...il.com>,
        <mark.rutland@....com>, <mingo@...hat.com>, <n.shubin@...ro.com>,
        <namhyung@...nel.org>, <palmer@...belt.com>,
        <paul.walmsley@...ive.com>, <peterlin@...estech.com>,
        <peterz@...radead.org>, <prabhakar.mahadev-lad.rj@...renesas.com>,
        <rdunlap@...radead.org>, <robh+dt@...nel.org>,
        <samuel@...lland.org>, <sunilvl@...tanamicro.com>,
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        <wens@...e.org>, <will@...nel.org>, <ycliang@...estech.com>
Subject: [PATCH v3 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string

Add "andestech,cpu-intc" compatible string which indicates that
Andes specific local interrupt is supported on the core,
e.g. AX45MP cores have 3 types of non-standard local interrupt
can be handled in supervisor mode:

- Slave port ECC error interrupt
- Bus write transaction error interrupt
- Performance monitor overflow interrupt

These interrupts are enabled/disabled via a custom register
SLIE instead of the standard interrupt enable register SIE.

Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
---
Changes v1 -> v2:
  - New patch
Changes v2 -> v3:
  - Updated commit message
  - Fixed possible compatibles for Andes INTC
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..4c1bbcf07406 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -99,7 +99,12 @@ properties:
         const: 1
 
       compatible:
-        const: riscv,cpu-intc
+        oneOf:
+          - items:
+              - enum:
+                  - andestech,cpu-intc
+              - const: riscv,cpu-intc
+          - const: riscv,cpu-intc
 
       interrupt-controller: true
 
-- 
2.34.1