lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZTjIGVE3o4K7O9kW@chao-email>
Date:   Wed, 25 Oct 2023 15:47:37 +0800
From:   Chao Gao <chao.gao@...el.com>
To:     Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
CC:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>, <x86@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Josh Poimboeuf <jpoimboe@...nel.org>,
        Andy Lutomirski <luto@...nel.org>,
        Jonathan Corbet <corbet@....net>,
        Sean Christopherson <seanjc@...gle.com>,
        Paolo Bonzini <pbonzini@...hat.com>, <tony.luck@...el.com>,
        <ak@...ux.intel.com>, <tim.c.chen@...ux.intel.com>,
        <linux-kernel@...r.kernel.org>, <linux-doc@...r.kernel.org>,
        <kvm@...r.kernel.org>,
        Alyssa Milburn <alyssa.milburn@...ux.intel.com>,
        Daniel Sneddon <daniel.sneddon@...ux.intel.com>,
        <antonio.gomez.iglesias@...ux.intel.com>
Subject: Re: [PATCH  v2 6/6] KVM: VMX: Move VERW closer to VMentry for MDS
 mitigation

On Tue, Oct 24, 2023 at 01:08:53AM -0700, Pawan Gupta wrote:
>During VMentry VERW is executed to mitigate MDS. After VERW, any memory
>access like register push onto stack may put host data in MDS affected
>CPU buffers. A guest can then use MDS to sample host data.
>
>Although likelihood of secrets surviving in registers at current VERW
>callsite is less, but it can't be ruled out. Harden the MDS mitigation
>by moving the VERW mitigation late in VMentry path.
>
>Note that VERW for MMIO Stale Data mitigation is unchanged because of
>the complexity of per-guest conditional VERW which is not easy to handle
>that late in asm with no GPRs available. If the CPU is also affected by
>MDS, VERW is unconditionally executed late in asm regardless of guest
>having MMIO access.
>
>Signed-off-by: Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>
>---
> arch/x86/kvm/vmx/vmenter.S |  4 ++++
> arch/x86/kvm/vmx/vmx.c     | 10 +++++++---
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
>diff --git a/arch/x86/kvm/vmx/vmenter.S b/arch/x86/kvm/vmx/vmenter.S
>index b3b13ec04bac..c566035938cc 100644
>--- a/arch/x86/kvm/vmx/vmenter.S
>+++ b/arch/x86/kvm/vmx/vmenter.S
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> #include <linux/linkage.h>
> #include <asm/asm.h>
>+#include <asm/segment.h>

This header is already included a few lines below:

#include <asm/nospec-branch.h>
#include <asm/percpu.h>
#include <asm/segment.h>	<---

> #include <asm/bitsperlong.h>
> #include <asm/kvm_vcpu_regs.h>
> #include <asm/nospec-branch.h>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ