linux-kernel - Re: [PATCH v1 1/1] ufs: core: Add host quirk QUIRK_MCQ_EXPAND_QUEUE

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Message-ID: <a16dc8ba-ca3b-4dd6-a8b5-dbb3ac7a49a5@acm.org>
Date:   Fri, 27 Oct 2023 13:55:20 -0700
From:   Bart Van Assche <bvanassche@....org>
To:     Chun-Hung Wu (巫駿宏) 
        <Chun-hung.Wu@...iatek.com>,
        "ebiggers@...gle.com" <ebiggers@...gle.com>,
        "quic_nguyenb@...cinc.com" <quic_nguyenb@...cinc.com>,
        "jejb@...ux.ibm.com" <jejb@...ux.ibm.com>,
        "avri.altman@....com" <avri.altman@....com>,
        "martin.petersen@...cle.com" <martin.petersen@...cle.com>,
        "quic_asutoshd@...cinc.com" <quic_asutoshd@...cinc.com>,
        "alim.akhtar@...sung.com" <alim.akhtar@...sung.com>,
        "Arthur.Simchaev@....com" <Arthur.Simchaev@....com>,
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        <angelogioacchino.delregno@...labora.com>,
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Cc:     Peter Wang (王信友) 
        <peter.wang@...iatek.com>,
        Eddie Huang (黃智傑) 
        <eddie.huang@...iatek.com>,
        Jiajie Hao (郝加节) 
        <jiajie.hao@...iatek.com>,
        CC Chou (周志杰) <cc.chou@...iatek.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Alice Chao (趙珮均) 
        <Alice.Chao@...iatek.com>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        wsd_upstream <wsd_upstream@...iatek.com>,
        Casper Li (李中榮) <casper.li@...iatek.com>,
        Tun-yu Yu (游敦聿) <Tun-yu.Yu@...iatek.com>,
        "linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>,
        Lin Gui (桂林) <Lin.Gui@...iatek.com>,
        Chaotian Jing (井朝天) 
        <Chaotian.Jing@...iatek.com>,
        Powen Kao (高伯文) <Powen.Kao@...iatek.com>,
        Naomi Chu (朱詠田) <Naomi.Chu@...iatek.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Qilin Tan (谭麒麟) <Qilin.Tan@...iatek.com>,
        "kernel-team@...roid.com" <kernel-team@...roid.com>
Subject: Re: [PATCH v1 1/1] ufs: core: Add host quirk
 QUIRK_MCQ_EXPAND_QUEUE_SLOT

On 10/26/23 20:27, Chun-Hung Wu (巫駿宏) wrote:
> From UFSHCI 4.0 spec "When the head and tail doorbells are equal, the
> queue is empty. *Nothe that this definition means there will always be
> one empty queue entry"
> One of our platform does not keep one empty queue
> entry for CQ full
> case, that's  why we need this patch to fix this corner case.

The UFSHCI driver should make sure that there is always one empty queue
entry. Does "platform" in the above text refer to the SoC that includes
the UFSHCI controller?

What is totally unclear to me is why the following code depends on the
UFSHCI controller type:

+		if (ufshcd_is_mcq_expand_queue_slot(hba))
+			hwq->max_entries = hba->nutrs + 1;
+		else
+			hwq->max_entries = hba->nutrs;

Shouldn't hwq->max_entries = hba->nutrs + 1 be used for all UFSHCI 4.0
controllers?

Thanks,

Bart.