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Message-ID: <877cn84jwo.ffs@tglx>
Date:   Fri, 27 Oct 2023 09:13:59 +0200
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Yu Chien Peter Lin <peterlin@...estech.com>, acme@...nel.org,
        adrian.hunter@...el.com, ajones@...tanamicro.com,
        alexander.shishkin@...ux.intel.com, andre.przywara@....com,
        anup@...infault.org, aou@...s.berkeley.edu, atishp@...shpatra.org,
        conor+dt@...nel.org, conor.dooley@...rochip.com, conor@...nel.org,
        devicetree@...r.kernel.org, dminus@...estech.com,
        evan@...osinc.com, geert+renesas@...der.be, guoren@...nel.org,
        heiko@...ech.de, irogers@...gle.com, jernej.skrabec@...il.com,
        jolsa@...nel.org, jszhang@...nel.org,
        krzysztof.kozlowski+dt@...aro.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-sunxi@...ts.linux.dev, locus84@...estech.com,
        magnus.damm@...il.com, mark.rutland@....com, mingo@...hat.com,
        n.shubin@...ro.com, namhyung@...nel.org, palmer@...belt.com,
        paul.walmsley@...ive.com, peterlin@...estech.com,
        peterz@...radead.org, prabhakar.mahadev-lad.rj@...renesas.com,
        rdunlap@...radead.org, robh+dt@...nel.org, samuel@...lland.org,
        sunilvl@...tanamicro.com, tim609@...estech.com, uwu@...nowy.me,
        wens@...e.org, will@...nel.org, ycliang@...estech.com
Subject: Re: [RFC PATCH v3 RESEND 03/13] irqchip/riscv-intc: Introduce Andes
 IRQ chip

On Mon, Oct 23 2023 at 08:40, Yu Chien Peter Lin wrote:
> +
> +	if (strcmp(cp, "riscv,cpu-intc") == 0)
> +		chip = &riscv_intc_chip;
> +	else if (strcmp(cp, "andestech,cpu-intc") == 0)
> +		chip = &andes_intc_chip;
> +	else
> +		return -ENXIO;

See the other reply.

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