linux-kernel - Re: [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes PMU extension description

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Message-ID: <ZTtlCEnbmVoPGj5l@APC323>
Date:   Fri, 27 Oct 2023 15:22:03 +0800
From:   Yu-Chien Peter Lin <peterlin@...estech.com>
To:     Conor Dooley <conor@...nel.org>
CC:     <acme@...nel.org>, <adrian.hunter@...el.com>,
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Subject: Re: [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes PMU
 extension description

On Thu, Oct 26, 2023 at 03:09:30PM +0100, Conor Dooley wrote:
> On Thu, Oct 26, 2023 at 04:22:22PM +0800, Yu-Chien Peter Lin wrote:
> > Hi Conor,
> > 
> > On Mon, Oct 23, 2023 at 01:03:53PM +0100, Conor Dooley wrote:
> > > On Mon, Oct 23, 2023 at 08:40:57AM +0800, Yu Chien Peter Lin wrote:
> > > > Document the ISA string for Andes Technology performance monitor
> > > > extension which provides counter overflow interrupt and mode
> > > > filtering mechanisms.
> > > > 
> > > > Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> > > > ---
> > > > Changes v2 -> v3:
> > > >   - New patch
> > > > ---
> > > >  Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
> > > >  1 file changed, 7 insertions(+)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > index 5e9291d258d5..e0694e2adbc2 100644
> > > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > @@ -246,6 +246,13 @@ properties:
> > > >              in commit 2e5236 ("Ztso is now ratified.") of the
> > > >              riscv-isa-manual.
> > > >  
> > > > +        - const: xandespmu
> > > > +          description:
> > > > +            The Andes Technology performance monitor extension for counter overflow
> > > > +            and privilege mode filtering. For more details, see Counter Related
> > > > +            Registers in the AX45MP datasheet.
> > > > +            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> > > 
> > > Does/will this PMU function identically on the other CPUs that support it?
> > 
> > Yes, I can confirm that.
> 
> If there's a more generic document available, that'd be good.

While it is currently the most comprehensive and publicly available
document we have, I will update it here once I obtain a more specific
version of the extension.

> Otherwise,
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>

Thanks for the review.

Regards,
Peter Lin

> 
> Thanks,
> Conor.