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Message-ID: <75b41aca-0333-4e69-aaf2-9aaa48d18d1b@linaro.org>
Date: Fri, 27 Oct 2023 10:18:35 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Sibi Sankar <quic_sibis@...cinc.com>, andersson@...nel.org,
konrad.dybcio@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, catalin.marinas@....com,
ulf.hansson@...aro.org
Cc: agross@...nel.org, conor+dt@...nel.org, ayan.kumar.halder@....com,
j@...nau.net, dmitry.baryshkov@...aro.org, nfraprado@...labora.com,
m.szyprowski@...sung.com, u-kumar1@...com, peng.fan@....com,
lpieralisi@...nel.org, quic_rjendra@...cinc.com,
abel.vesa@...aro.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, quic_tsoni@...cinc.com,
neil.armstrong@...aro.org
Subject: Re: [PATCH 5/5] arm64: defconfig: Enable SC8380XP SoC base configs
On 25/10/2023 16:24, Sibi Sankar wrote:
> From: Rajendra Nayak <quic_rjendra@...cinc.com>
>
> Enable GCC, Pinctrl and Interconnect configs for SC8380XP needed to boot
> to a console shell.
This is generic defconfig for all platforms. You must be explicit which
SoC and board you now target. How anyone could figure out that random
set of numbers/letters like A1204XZY SoC is Qualcomm?
Best regards,
Krzysztof
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