lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-Id: <169841282922.15670.7049548367508629850.git-patchwork-notify@kernel.org>
Date:   Fri, 27 Oct 2023 13:20:29 +0000
From:   patchwork-bot+linux-riscv@...nel.org
To:     Anup Patel <apatel@...tanamicro.com>
Cc:     linux-riscv@...ts.infradead.org, palmer@...belt.com,
        paul.walmsley@...ive.com, daniel.lezcano@...aro.org,
        tglx@...utronix.de, anup@...infault.org,
        linux-kernel@...r.kernel.org, conor@...nel.org,
        atishp@...shpatra.org, ajones@...tanamicro.com
Subject: Re: [PATCH 0/2] Misc RISC-V timer driver improvements

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@...osinc.com>:

On Mon, 10 Jul 2023 18:49:00 +0530 you wrote:
> This series does two improvements to the RISC-V timer driver:
> 1) Keep timer interrupt enable state in-sync with interrupt subsystem
> 2) Increase rating of clock event device when Sstc is available
> 
> These patches can also be found in the riscv_timer_imp_v1 branch at:
> https://github.com/avpatel/linux.git
> 
> [...]

Here is the summary with links:
  - [1/2] clocksource: timer-riscv: Don't enable/disable timer interrupt
    https://git.kernel.org/riscv/c/d39d86e3e78b
  - [2/2] clocksource: timer-riscv: Increase rating of clock_event_device for Sstc
    https://git.kernel.org/riscv/c/fde893ef7084

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ