linux-kernel - Re: [POC][RFC][PATCH v2] sched: Extended Scheduler Time Slice

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Message-ID: <0b88d73c-c1c0-4ed8-9e63-b54698fbc039@efficios.com>
Date:   Fri, 27 Oct 2023 12:21:45 -0400
From:   Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
To:     Steven Rostedt <rostedt@...dmis.org>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ankur Arora <ankur.a.arora@...cle.com>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        linux-mm@...ck.org, x86@...nel.org, akpm@...ux-foundation.org,
        luto@...nel.org, bp@...en8.de, dave.hansen@...ux.intel.com,
        hpa@...or.com, mingo@...hat.com, juri.lelli@...hat.com,
        vincent.guittot@...aro.org, willy@...radead.org, mgorman@...e.de,
        jon.grimm@....com, bharata@....com, raghavendra.kt@....com,
        boris.ostrovsky@...cle.com, konrad.wilk@...cle.com,
        jgross@...e.com, andrew.cooper3@...rix.com,
        Joel Fernandes <joel@...lfernandes.org>,
        Youssef Esmat <youssefesmat@...omium.org>,
        Vineeth Pillai <vineethrp@...gle.com>,
        Suleiman Souhlal <suleiman@...gle.com>,
        Ingo Molnar <mingo@...nel.org>,
        Daniel Bristot de Oliveira <bristot@...nel.org>
Subject: Re: [POC][RFC][PATCH v2] sched: Extended Scheduler Time Slice

On 2023-10-26 17:35, Steven Rostedt wrote:
> On Thu, 26 Oct 2023 15:20:22 -0400
> Steven Rostedt <rostedt@...dmis.org> wrote:
> 
>> Anyway, I changed the code to use:
>>
>> static inline unsigned clrbit(volatile unsigned *ptr)
>> {
>> 	unsigned ret;
>>
>> 	asm volatile("andb %b1,%0"
>> 		     : "+m" (*(volatile char *)ptr)
>> 		     : "iq" (0x2)
>> 		     : "memory");
>>
>> 	ret = *ptr;
>> 	*ptr = 0;
>>
>> 	return ret;
>> }
> 
> Mathieu also told me that glibc's rseq has some extra padding at the end,
> that happens to be big enough to hold this feature. That means you can run
> the code without adding:
> 
>    GLIBC_TUNABLES=glibc.pthread.rseq=0
> 
> Attached is the updated test program.

I think you'll want to modify the semantic of your "cr_flags" field so
it supports nested locks as well. You can change this cr_flags for a
nesting counter. The "yield" bit could be one of the bits of that
counter (e.g. lowest bit).

Therefore extend() become add 0x2, and unextend() become a sub 0x2, and
you can check the lowest bit for yield hint.

Thanks,

Mathieu

-- 
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com