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Message-ID: <8ff0355a-7ed3-4f15-9ad7-350e6094f00f@amd.com>
Date: Mon, 6 Nov 2023 10:51:01 -0600
From: Mario Limonciello <mario.limonciello@....com>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: Karol Herbst <kherbst@...hat.com>, Lyude Paul <lyude@...hat.com>,
Alex Deucher <alexander.deucher@....com>,
Christian König <christian.koenig@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Hans de Goede <hdegoede@...hat.com>,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
Lukas Wunner <lukas@...ner.de>,
Danilo Krummrich <dakr@...hat.com>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Xinhui Pan <Xinhui.Pan@....com>,
"Rafael J . Wysocki" <rafael@...nel.org>,
Mark Gross <markgross@...nel.org>,
Andreas Noever <andreas.noever@...il.com>,
Michael Jamet <michael.jamet@...el.com>,
Yehezkel Bernat <YehezkelShB@...il.com>,
Pali Rohár <pali@...nel.org>,
Marek Behún <kabel@...nel.org>,
"Maciej W . Rozycki" <macro@...am.me.uk>,
Manivannan Sadhasivam <mani@...nel.org>,
"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
<dri-devel@...ts.freedesktop.org>,
"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
<nouveau@...ts.freedesktop.org>,
open list <linux-kernel@...r.kernel.org>,
"open list:RADEON and AMDGPU DRM DRIVERS"
<amd-gfx@...ts.freedesktop.org>,
"open list:PCI SUBSYSTEM" <linux-pci@...r.kernel.org>,
"open list:ACPI" <linux-acpi@...r.kernel.org>,
"open list:X86 PLATFORM DRIVERS"
<platform-driver-x86@...r.kernel.org>,
"open list:THUNDERBOLT DRIVER" <linux-usb@...r.kernel.org>
Subject: Re: [PATCH v2 8/9] PCI: Exclude PCIe ports used for tunneling in
pcie_bandwidth_available()
On 11/6/2023 06:52, Ilpo Järvinen wrote:
> On Fri, 3 Nov 2023, Mario Limonciello wrote:
>
>> The USB4 spec specifies that PCIe ports that are used for tunneling
>> PCIe traffic over USB4 fabric will be hardcoded to advertise 2.5GT/s and
>> behave as a PCIe Gen1 device. The actual performance of these ports is
>> controlled by the fabric implementation.
>>
>> Downstream drivers such as amdgpu which utilize pcie_bandwidth_available()
>> to program the device will always find the PCIe ports used for
>> tunneling as a limiting factor potentially leading to incorrect
>> performance decisions.
>>
>> To prevent problems in downstream drivers check explicitly for ports
>> being used for PCIe tunneling and skip them when looking for bandwidth
>> limitations of the hierarchy. If the only device connected is a root port
>> used for tunneling then report that device.
>>
>> Downstream drivers could make this change on their own but then they
>> wouldn't be able to detect other potential speed bottlenecks from the
>> hierarchy without duplicating pcie_bandwidth_available() logic.
>>
>> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925#note_2145860
>> Link: https://www.usb.org/document-library/usb4r-specification-v20
>> USB4 V2 with Errata and ECN through June 2023
>> Section 11.2.1
>> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
>> ---
>> drivers/pci/pci.c | 74 +++++++++++++++++++++++++++++++----------------
>> 1 file changed, 49 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
>> index d9aa5a39f585..15e37164ce56 100644
>> --- a/drivers/pci/pci.c
>> +++ b/drivers/pci/pci.c
>> @@ -6223,6 +6223,35 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
>> }
>> EXPORT_SYMBOL(pcie_set_mps);
>>
>> +static u32 pcie_calc_bw_limits(struct pci_dev *dev, u32 bw,
>> + struct pci_dev **limiting_dev,
>> + enum pci_bus_speed *speed,
>> + enum pcie_link_width *width)
>> +{
>> + enum pcie_link_width next_width;
>> + enum pci_bus_speed next_speed;
>> + u32 next_bw;
>> + u16 lnksta;
>> +
>> + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
>> + next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
>> + next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
>> + next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
>> +
>> + /* Check if current device limits the total bandwidth */
>> + if (!bw || next_bw <= bw) {
>> + bw = next_bw;
>> + if (limiting_dev)
>> + *limiting_dev = dev;
>> + if (speed)
>> + *speed = next_speed;
>> + if (width)
>> + *width = next_width;
>> + }
>> +
>> + return bw;
>> +}
>> +
>> /**
>> * pcie_bandwidth_available - determine minimum link settings of a PCIe
>> * device and its bandwidth limitation
>> @@ -6236,47 +6265,42 @@ EXPORT_SYMBOL(pcie_set_mps);
>> * limiting_dev, speed, and width pointers are supplied) information about
>> * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
>> * raw bandwidth.
>> + *
>> + * This excludes the bandwidth calculation that has been returned from a
>> + * PCIe device used for transmitting tunneled PCIe traffic over a Thunderbolt
>> + * or USB4 link that is part of larger hierarchy. The calculation is excluded
>> + * because the USB4 specification specifies that the max speed returned from
>> + * PCIe configuration registers for the tunneling link is always PCI 1x 2.5 GT/s.
>> + * When only tunneled devices are present, the bandwidth returned is the
>> + * bandwidth available from the first tunneled device.
>> */
>> u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
>> enum pci_bus_speed *speed,
>> enum pcie_link_width *width)
>> {
>> - u16 lnksta;
>> - enum pci_bus_speed next_speed;
>> - enum pcie_link_width next_width;
>> - u32 bw, next_bw;
>> + struct pci_dev *tdev = NULL;
>> + u32 bw = 0;
>>
>> if (speed)
>> *speed = PCI_SPEED_UNKNOWN;
>> if (width)
>> *width = PCIE_LNK_WIDTH_UNKNOWN;
>>
>> - bw = 0;
>> -
>> while (dev) {
>> - pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
>> -
>> - next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
>> - next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
>> - PCI_EXP_LNKSTA_NLW_SHIFT;
>> -
>> - next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
>> -
>> - /* Check if current device limits the total bandwidth */
>> - if (!bw || next_bw <= bw) {
>> - bw = next_bw;
>> -
>> - if (limiting_dev)
>> - *limiting_dev = dev;
>> - if (speed)
>> - *speed = next_speed;
>> - if (width)
>> - *width = next_width;
>> + if (dev->is_tunneled) {
>> + if (!tdev)
>> + tdev = dev;
>> + goto skip;
>> }
>> -
>> + bw = pcie_calc_bw_limits(dev, bw, limiting_dev, speed, width);
>> +skip:
>> dev = pci_upstream_bridge(dev);
>> }
>>
>> + /* If nothing "faster" found on link, limit to first tunneled device */
>> + if (tdev && !bw)
>> + bw = pcie_calc_bw_limits(tdev, bw, limiting_dev, speed, width);
>> +
>> return bw;
>> }
>> EXPORT_SYMBOL(pcie_bandwidth_available);
>>
>
> This patch should be split into two, where one just moves the code to the
> new function.
Good idea, thanks.
>
> Also note that this will conflict with the FIELD_GET() changes (try to
> not reintroduce non-FIELD_GET() code when you rebase this on top of
> v6.7-rc1 :-)).
>
Sure, will adjust for that when it's rebased to 6.7-rc1.
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