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Message-ID: <CAD=FV=XOyHr9hNA0gEdssGz5qqyXHU75K9TUH3HSHK3+jpfswg@mail.gmail.com>
Date: Mon, 6 Nov 2023 08:53:59 -0800
From: Doug Anderson <dianders@...omium.org>
To: Ankit Sharma <quic_anshar@...cinc.com>
Cc: cros-qcom-dts-watchers@...omium.org, agross@...nel.org,
andersson@...nel.org, konrad.dybcio@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, quic_ashayj@...cinc.com,
quic_atulpant@...cinc.com, quic_rgottimu@...cinc.com,
quic_shashim@...cinc.com, quic_pkondeti@...cinc.com
Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Add capacity and DPC properties
Hi,
On Fri, Nov 3, 2023 at 3:54 AM Ankit Sharma <quic_anshar@...cinc.com> wrote:
>
> The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
> used to build Energy Model which in turn is used by EAS to take
> placement decisions. So add it to SC7280 soc.
>
> Signed-off-by: Ankit Sharma <quic_anshar@...cinc.com>
> ---
> changes in v2: https://lore.kernel.org/all/20231103095358.29312-1-quic_anshar@quicinc.com/
> - updated commit message and subject.
>
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 8601253aec70..b1890824188c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -176,6 +176,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_0>;
> operating-points-v2 = <&cpu0_opp_table>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -204,6 +206,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_100>;
> operating-points-v2 = <&cpu0_opp_table>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -227,6 +231,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_200>;
> operating-points-v2 = <&cpu0_opp_table>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -250,6 +256,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_300>;
> operating-points-v2 = <&cpu0_opp_table>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -273,6 +281,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_400>;
> operating-points-v2 = <&cpu4_opp_table>;
> + capacity-dmips-mhz = <1946>;
Though I don't think it's technically required, in other systems
(including the examples in the documentation) the biggest CPU gets
1024 "capacity-dmips-mhz" and the other ones are scaled to that.
> + dynamic-power-coefficient = <520>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> @@ -296,6 +306,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_500>;
> operating-points-v2 = <&cpu4_opp_table>;
> + capacity-dmips-mhz = <1946>;
> + dynamic-power-coefficient = <520>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> @@ -319,6 +331,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_600>;
> operating-points-v2 = <&cpu4_opp_table>;
> + capacity-dmips-mhz = <1946>;
> + dynamic-power-coefficient = <520>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> @@ -342,6 +356,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_700>;
> operating-points-v2 = <&cpu7_opp_table>;
> + capacity-dmips-mhz = <1985>;
> + dynamic-power-coefficient = <552>;
The fact that cpu7 has different values for capacity-dmips-mhz and
dynamic-power-coefficient is surprising to me. I think what this means
is that at the same MHz this core can process more instructions than
the other big CPUs but that (at the same MHz) it burns more power
doing so. Is that really true? I thought that this core was
essentially the same as the other big cores but was simply anointed to
be able to run a little faster.
-Doug
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