[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <0f76a5c1-14ce-cbfa-bbd9-b2826c4bbbdb@quicinc.com>
Date: Tue, 7 Nov 2023 14:25:25 +0530
From: Mukesh Ojha <quic_mojha@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] dt-bindings: cache: qcom,llcc: correct QDU1000 reg
entries
On 11/7/2023 1:34 PM, Krzysztof Kozlowski wrote:
> Qualcomm QDU1000 DTSI comes with one LLCC0 base address as pointed by
> dtbs_check:
>
> qdu1000-idp.dtb: system-cache-controller@...00000: reg-names:2: 'llcc2_base' was expected
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>
> ---
>
> Recent LLCC patches were not tested on QDU1000 thus the LLCC is there
> broken. This patch at least tries to bring some sense according to
> DTSI, but I have no clue what is here correct: driver, DTS or bindings.
> ---
> Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> index 580f9a97ddf7..d610b0be262c 100644
> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> @@ -64,6 +64,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,qdu1000-llcc
> - qcom,sc7180-llcc
> - qcom,sm6350-llcc
Thanks, again.
Acked-by: Mukesh Ojha <quic_mojha@...cinc.com>
-Mukesh
> then:
> @@ -101,7 +102,6 @@ allOf:
> compatible:
> contains:
> enum:
> - - qcom,qdu1000-llcc
> - qcom,sc8180x-llcc
> - qcom,sc8280xp-llcc
> then:
Powered by blists - more mailing lists