linux-kernel - Re: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default event on certain Zen2 processors

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Message-ID: <CAM9d7cgs9Wk0OFoea4jOote-drHjvCimJyt7GWdO2Giw=d7Jog@mail.gmail.com>
Date:   Thu, 9 Nov 2023 13:53:22 -0800
From:   Namhyung Kim <namhyung@...nel.org>
To:     Ravi Bangoria <ravi.bangoria@....com>
Cc:     acme@...nel.org, kim.phillips@....com, peterz@...radead.org,
        mingo@...hat.com, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
        irogers@...gle.com, adrian.hunter@...el.com,
        kan.liang@...ux.intel.com, changbin.du@...wei.com,
        yangjihong1@...wei.com, zwisler@...omium.org,
        wangming01@...ngson.cn, chenhuacai@...nel.org,
        kprateek.nayak@....com, linux-perf-users@...r.kernel.org,
        linux-kernel@...r.kernel.org, sandipan.das@....com,
        ananth.narayan@....com, santosh.shukla@....com
Subject: Re: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default
 event on certain Zen2 processors

Hi Ravi,

On Tue, Nov 7, 2023 at 12:34 AM Ravi Bangoria <ravi.bangoria@....com> wrote:
>
> By default, Perf uses precise cycles event when no explicit event is
> specified by user. Precise cycles event is forwarded to ibs_op// pmu
> on AMD. However, IBS has hw issue on certain Zen2 processors where
> it might raise NMI without sample_valid bit set, which causes Unknown
> NMI warnings. (Erratum #1215: IBS (Instruction Based Sampling) Counter
> Valid Value May be Incorrect After Exit From Core C6 (CC6) State.) So,
> use non-precise cycles as default event on affected processors.

It seems like a kernel issue, do we have a kernel patch not to forward
precise cycles or instructions events to IBS on the affected CPUs?

Thanks,
Namhyung

>
> This does not prevent user to use explicit precise cycles event or
> ibs_op// pmu directly.
>
> Suggested-by: Arnaldo Carvalho de Melo <acme@...nel.org>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@....com>
> ---