linux-kernel - Re: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default event on certain Zen2 processors

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Message-ID: <5a9974ba-1c64-a120-7641-5bd1f12c9caf@amd.com>
Date:   Fri, 10 Nov 2023 15:07:15 +0530
From:   Ravi Bangoria <ravi.bangoria@....com>
To:     Ian Rogers <irogers@...gle.com>
Cc:     acme@...nel.org, namhyung@...nel.org, kim.phillips@....com,
        peterz@...radead.org, mingo@...hat.com, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
        adrian.hunter@...el.com, kan.liang@...ux.intel.com,
        changbin.du@...wei.com, yangjihong1@...wei.com,
        zwisler@...omium.org, wangming01@...ngson.cn,
        chenhuacai@...nel.org, kprateek.nayak@....com,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
        sandipan.das@....com, ananth.narayan@....com,
        santosh.shukla@....com, Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default
 event on certain Zen2 processors

Hi Ian,

> We read max_precise from sysfs:
> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/pmu.c?h=perf-tools-next#n984
> 
> But it appears not to be used:
> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/util/evsel.c?h=perf-tools-next#n1323
> 
> I think:
> ```
> if (evsel->precise_max)
>     attr->precise_ip = 3;
> ```
> should be:
> ```
> if (evsel->precise_max)
>     attr->precise_ip = evsel->pmu->max_precise;
> ```

This segfaults as evsel->pmu is NULL. But I get your point.

If we go with this change, I'll need to switch to cycles:p as default
event on AMD. Otherwise perf will use non-precise event as default event
on AMD.

> Presumably this is misreporting as some non-zero value on the buggy
> systems - if it doesn't we can declare victory here. If not we can
> modify max_precise's calculation on perf's struct pmu for cpu for AMD
> so that we just hardwire it to zero in arch code.

max_precise for AMD core pmu is 0, which is correct as AMD core pmu does
not support precise mode. However, cycles:p, r76:p and rC1:p are special
cases and allowed via core pmu.

Thanks,
Ravi