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Message-ID: <f42bf6b7-75b8-124b-c79e-ad7a9b706990@amd.com>
Date:   Fri, 10 Nov 2023 15:16:08 +0530
From:   Ravi Bangoria <ravi.bangoria@....com>
To:     Namhyung Kim <namhyung@...nel.org>
Cc:     acme@...nel.org, kim.phillips@....com, peterz@...radead.org,
        mingo@...hat.com, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
        irogers@...gle.com, adrian.hunter@...el.com,
        kan.liang@...ux.intel.com, changbin.du@...wei.com,
        yangjihong1@...wei.com, zwisler@...omium.org,
        wangming01@...ngson.cn, chenhuacai@...nel.org,
        kprateek.nayak@....com, linux-perf-users@...r.kernel.org,
        linux-kernel@...r.kernel.org, sandipan.das@....com,
        ananth.narayan@....com, santosh.shukla@....com,
        Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default
 event on certain Zen2 processors

Hi Namhyung,

>> By default, Perf uses precise cycles event when no explicit event is
>> specified by user. Precise cycles event is forwarded to ibs_op// pmu
>> on AMD. However, IBS has hw issue on certain Zen2 processors where
>> it might raise NMI without sample_valid bit set, which causes Unknown
>> NMI warnings. (Erratum #1215: IBS (Instruction Based Sampling) Counter
>> Valid Value May be Incorrect After Exit From Core C6 (CC6) State.) So,
>> use non-precise cycles as default event on affected processors.
> 
> It seems like a kernel issue, do we have a kernel patch not to forward
> precise cycles or instructions events to IBS on the affected CPUs?

I'm not sure how it's a kernel issue. User can use ibs_op// pmu directly
and might hit the hw bug.

Thanks,
Ravi

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