[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAM9d7cijrZzp=5m+BcQ77WFOSHT7e5vO-RCUTUp5Pevmz2wbtg@mail.gmail.com>
Date: Fri, 8 Dec 2023 15:33:26 -0800
From: Namhyung Kim <namhyung@...nel.org>
To: Ravi Bangoria <ravi.bangoria@....com>
Cc: acme@...nel.org, kim.phillips@....com, peterz@...radead.org,
mingo@...hat.com, mark.rutland@....com,
alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
irogers@...gle.com, adrian.hunter@...el.com,
kan.liang@...ux.intel.com, changbin.du@...wei.com,
yangjihong1@...wei.com, zwisler@...omium.org,
wangming01@...ngson.cn, chenhuacai@...nel.org,
kprateek.nayak@....com, linux-perf-users@...r.kernel.org,
linux-kernel@...r.kernel.org, sandipan.das@....com,
ananth.narayan@....com, santosh.shukla@....com
Subject: Re: [PATCH 1/2] perf tool AMD: Use non-precise cycles as default
event on certain Zen2 processors
Hi Ravi,
On Fri, Nov 10, 2023 at 1:46 AM Ravi Bangoria <ravi.bangoria@....com> wrote:
>
> Hi Namhyung,
>
> >> By default, Perf uses precise cycles event when no explicit event is
> >> specified by user. Precise cycles event is forwarded to ibs_op// pmu
> >> on AMD. However, IBS has hw issue on certain Zen2 processors where
> >> it might raise NMI without sample_valid bit set, which causes Unknown
> >> NMI warnings. (Erratum #1215: IBS (Instruction Based Sampling) Counter
> >> Valid Value May be Incorrect After Exit From Core C6 (CC6) State.) So,
> >> use non-precise cycles as default event on affected processors.
> >
> > It seems like a kernel issue, do we have a kernel patch not to forward
> > precise cycles or instructions events to IBS on the affected CPUs?
>
> I'm not sure how it's a kernel issue. User can use ibs_op// pmu directly
> and might hit the hw bug.
Sorry for the late reply. I know it's the user's fault when using ibs_op//
directly but I think the kernel should not forward cycles:pp to IBS.
Thanks,
Namhyung
Powered by blists - more mailing lists