linux-kernel - Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller node

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <b40a74f4-1605-d3a1-2c6a-845c41419442@quicinc.com>
Date:   Fri, 10 Nov 2023 10:33:08 +0530
From:   Mrinmay Sarkar <quic_msarkar@...cinc.com>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Andrew Halaney <ahalaney@...hat.com>
CC:     <agross@...nel.org>, <andersson@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <mani@...nel.org>, <robh+dt@...nel.org>,
        <quic_shazhuss@...cinc.com>, <quic_nitegupt@...cinc.com>,
        <quic_ramkri@...cinc.com>, <quic_nayiluri@...cinc.com>,
        <dmitry.baryshkov@...aro.org>, <robh@...nel.org>,
        <quic_krichai@...cinc.com>, <quic_vbadigan@...cinc.com>,
        <quic_parass@...cinc.com>, <quic_schintav@...cinc.com>,
        <quic_shijjose@...cinc.com>, Vinod Koul <vkoul@...nel.org>,
        "Kishon Vijay Abraham I" <kishon@...nel.org>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>
Subject: Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Add ep pcie1 controller
 node


On 11/8/2023 3:24 AM, Konrad Dybcio wrote:
>
>
> On 11/7/23 19:37, Andrew Halaney wrote:
>> On Tue, Nov 07, 2023 at 06:34:53PM +0530, Mrinmay Sarkar wrote:
>>> Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
>>> It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
>>> stability issues.
>>
>> I wouldn't mind a bit more information on what "stability" issues
>> entails! I'm a sucker for details in a commit message.
> Yep, giving us a bit more than "doesnt work" may help us help you!
Actually if I enable gen4 some time I am getting link down and sometime
link getting establish at gen1. I am not getting stable gen4, may be we
need to program some register to get stable gen4 that I am checking.
>>> +
>>> +        interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
>>> +                     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
>>> +                     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
> Looks like the indentation is off?
>
>>> +
>>> +        interrupt-names = "global", "doorbell", "dma";
>>> +
>>> +        interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt 
>>> SLAVE_EBI1 0>,
>>> +                <&gem_noc MASTER_APPSS_PROC 0 &config_noc 
>>> SLAVE_PCIE_1 0>;
>>
>> I keep seeing Konrad requesting that we use the #define instead of a raw
>> number 0, i.e. something like QCOM_ICC_TAG_ALWAYS (although if I'm
>> reading that correctly QCOM_ICC_TAG_ALWAYS doesn't evaluate to 0, so
>> make sure you pick the appropriate one).
> No it doesn't, but if you look at the code, tag being non-existent
> assigns QCOM_ICC_TAG_ALWAYS which is a workaround for DTBs from back
> when interconnect tags were not a thing
>
>>
>>> +        interconnect-names = "pcie-mem", "cpu-pcie";
>>
>> This is nitpicky, but unless someone told you to do the whitespace
>> between some of these properties I'd get more consistent. i.e. reg and
>> reg-names has no newline between them, but clocks and clock-names does,
>> and then interconnects/interconnect-names does not.
> :)
I don't think there is any rule to add those white spaces, in next patch
I will align these white spaces with other pcie nodes.
>
> Konrad

Thanks,
Mrinmay