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Message-ID: <CACRpkdbPWxQMz_1gG1He5QN65BActhyea_KBv2cyQ_VQxc6Feg@mail.gmail.com>
Date: Mon, 13 Nov 2023 15:15:58 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: "larry.lai" <larry.lai@...jingtech.com>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: lee@...nel.org, pavel@....cz, linux-kernel@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-leds@...r.kernel.org,
GaryWang@...on.com.tw, musa.lin@...jingtech.com,
jack.chang@...jingtech.com, noah.hung@...jingtech.com
Subject: Re: [PATCH V7 2/3] pinctrl: Add support pin control for UP board CPLD/FPGA
Hi Larry, Andy,
On Tue, Oct 31, 2023 at 2:51 AM larry.lai <larry.lai@...jingtech.com> wrote:
> The UP Squared board <http://www.upboard.com> implements certain
> features (pin control) through an on-board FPGA.
>
> Reported-by: kernel test robot <lkp@...el.com>
> Signed-off-by: Gary Wang <garywang@...on.com.tw>
> Signed-off-by: larry.lai <larry.lai@...jingtech.com>
(...)
> +#include "core.h"
> +#include "intel/pinctrl-intel.h"
As mentioned this is using the intel core pin control driver infrastructure
so I want Andy's ACK on this before I merge it.
Yours,
Linus Walleij
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