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Date:   Fri, 17 Nov 2023 01:40:46 +0000
From:   Thinh Nguyen <Thinh.Nguyen@...opsys.com>
To:     "20231116174206.1a823aa3@...opsys.com" 
        <20231116174206.1a823aa3@...opsys.com>
CC:     Jisheng Zhang <jszhang@...nel.org>,
        Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Lu jicong <jiconglu58@...il.com>,
        "linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH] usb: dwc3: don't reset device side if dwc3 was configured
 as host-only

Hi,

On Thu, Nov 16, 2023, Köry Maincent wrote:
> On Thu, 16 Nov 2023 17:42:06 +0100
> Köry Maincent <kory.maincent@...tlin.com> wrote:
> 
> > Hello,
> > 
> > Similar issue with ZynqMP board related to that patch:
> > 
> > xilinx-psgtr fd400000.phy: lane 3 (type 1, protocol 3): PLL lock timeout
> > phy phy-fd400000.phy.3: phy poweron failed --> -110
> > dwc3 fe300000.usb: error -ETIMEDOUT: failed to initialize core
> > 
> > With CONFIG_USB_DWC3_DUAL_ROLE and dr_mode = "host";
> > 
> > It may not be the correct fix.
> 
> Just figured out there was a patch (357191036889 usb: dwc3: Soft reset phy on
> probe for host) from Thinh aimed to fix it but the issue is still here on
> ZynqMP.
> 

How many ports do you use? Can you try this:

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 0328c86ef806..9921c2737829 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -296,23 +296,28 @@ int dwc3_core_soft_reset(struct dwc3 *dwc)
 	if (dwc->dr_mode == USB_DR_MODE_HOST) {
 		u32 usb3_port;
 		u32 usb2_port;
+		int i;
 
-		usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
-		usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
-		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
+		for (i = 0; i < 16; i++) {
+			usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
+			usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
+			dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), usb3_port);
 
-		usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-		usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
-		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
+			usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+			usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
+			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), usb2_port);
+		}
 
 		/* Small delay for phy reset assertion */
 		usleep_range(1000, 2000);
 
-		usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
-		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
+		for (i = 0; i < 16; i++) {
+			usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
+			dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), usb3_port);
 
-		usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
-		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
+			usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
+			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), usb2_port);
+		}
 
 		/* Wait for clock synchronization */
 		msleep(50);
---

BR,
Thinh

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