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Message-ID: <86e165a-fcce-4877-c59a-afaeefd9a42d@linux-m68k.org>
Date: Tue, 21 Nov 2023 11:17:11 +0100 (CET)
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu <claudiu.beznea@...on.dev>
cc: tglx@...utronix.de, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
magnus.damm@...il.com, mturquette@...libre.com, sboyd@...nel.org,
prabhakar.mahadev-lad.rj@...renesas.com,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when
writing ISCR register
On Mon, 20 Nov 2023, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes
> the operation to clear interrupts through the ISCR register as follows:
>
> [Write operation]
> When "Falling-edge detection", "Rising-edge detection" or
> "Falling/Rising-edge detection" is set in IITSR:
> - In case ISTAT is 1
> 0: IRQn interrupt detection status is cleared.
> 1: Invalid to write.
> - In case ISTAT is 0
> Invalid to write.
>
> When “Low-level detection” is set in IITSR.:
> Invalid to write.
>
> Take the interrupt type into account when clearing interrupts through
> the ISCR register to avoid writing the ISCR when interrupt type is
> level.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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