linux-kernel - Re: [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index

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Date:   Tue, 21 Nov 2023 11:30:02 +0100 (CET)
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     Claudiu <claudiu.beznea@...on.dev>
cc:     tglx@...utronix.de, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        magnus.damm@...il.com, mturquette@...libre.com, sboyd@...nel.org,
        prabhakar.mahadev-lad.rj@...renesas.com,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org,
        Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve
 TITSR register offset based on register's index

 	Hi Claudiu,

Thanks for your patch!

On Mon, 20 Nov 2023, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> There are 2 TITSR registers available on IA55 interrupt controller. A

... the IA55 interrupt controller.

> single macro could be used to access both of them. Add a macro that
> retrieves TITSR register offset based on it's index. This macro is

the TITSR register offset ... its index

> useful in commit that adds suspend/resume support to access both TITSR

> registers in a for loop.

This macro will be useful to access both TITSR registers in a for loop
when adding suspend/resume support later/

>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>

> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -28,8 +28,7 @@
> #define ISCR				0x10
> #define IITSR				0x14
> #define TSCR				0x20
> -#define TITSR0				0x24
> -#define TITSR1				0x28
> +#define TITSR(n)			(0x24 + (n) * 4)
> #define TITSR0_MAX_INT			16
> #define TITSEL_WIDTH			0x2
> #define TSSR(n)				(0x30 + ((n) * 4))
> @@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
> 	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> 	unsigned int hwirq = irqd_to_hwirq(d);
> 	u32 titseln = hwirq - IRQC_TINT_START;
> -	u32 offset;
> -	u8 sense;
> +	u8 index, sense;
> 	u32 reg;
>
> 	switch (type & IRQ_TYPE_SENSE_MASK) {
> @@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
> 		return -EINVAL;
> 	}
>
> -	offset = TITSR0;
> +	index = 0;
> 	if (titseln >= TITSR0_MAX_INT) {
> 		titseln -= TITSR0_MAX_INT;
> -		offset = TITSR1;
> +		index = 1;
> 	}

You can remove this if you would use ...
>
> 	raw_spin_lock(&priv->lock);
> -	reg = readl_relaxed(priv->base + offset);
> +	reg = readl_relaxed(priv->base + TITSR(index));

... TITSR(titseln / TITSR0_MAX_INT) here.

> 	reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
> 	reg |= sense << (titseln * TITSEL_WIDTH);
> -	writel_relaxed(reg, priv->base + offset);
> +	writel_relaxed(reg, priv->base + TITSR(index));
> 	raw_spin_unlock(&priv->lock);
>
> 	return 0;
> -- 
> 2.39.2
>
>

Gr{oetje,eeting}s,

 						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
 							    -- Linus Torvalds