linux-kernel - Re: [PATCH v1 1/2] dt-bindings: phy: Add starfive,jh7110-dphy-tx

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Message-ID: <c2d818fd-9dad-4beb-82a5-caf30f146bb5@starfivetech.com>
Date:   Thu, 23 Nov 2023 14:53:36 +0800
From:   Shengyang Chen <shengyang.chen@...rfivetech.com>
To:     Rob Herring <robh@...nel.org>
CC:     <devicetree@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
        <vkoul@...nel.org>, <kishon@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <p.zabel@...gutronix.de>, <minda.chen@...rfivetech.com>,
        <changhuang.liang@...rfivetech.com>, <rogerq@...nel.org>,
        <geert+renesas@...der.be>, <keith.zhao@...rfivetech.com>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 1/2] dt-bindings: phy: Add starfive,jh7110-dphy-tx

Dear Rob,

Thank you for your review and comment

On 2023/11/20 0:09, Rob Herring wrote:
> On Fri, Nov 17, 2023 at 09:04:20PM +0800, Shengyang Chen wrote:
>> StarFive SoCs like the jh7110 use a MIPI D-PHY TX
>> controller based on a M31 IP. Add a binding for it.
>> 
>> Signed-off-by: Shengyang Chen <shengyang.chen@...rfivetech.com>
>> ---
>>  .../bindings/phy/starfive,jh7110-dphy-tx.yaml | 74 +++++++++++++++++++
>>  1 file changed, 74 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
>> new file mode 100644
>> index 000000000000..850fe2e61d1d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
>> @@ -0,0 +1,74 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Starfive SoC MIPI D-PHY Tx Controller
>> +
>> +maintainers:
>> +  - Keith Zhao <keith.zhao@...rfivetech.com>
>> +  - Shengyang Chen <shengyang.chen@...rfivetech.com>
>> +
>> +description:
>> +  The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer
>> +  DSI data.
>> +
>> +properties:
>> +  compatible:
>> +    const: starfive,jh7110-dphy-tx
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  clock-names:
>> +    items:
>> +      - const: dphy_txesc
> 
> Module name is redundant. Drop 'dphy_'.
> 

OK, will drop "dphy_".

>> +
>> +  resets:
>> +    items:
>> +      - description: DSITX_TXBYTEHS reset
>> +      - description: MIPITX_DPHY_SYS reset
>> +      - description: MIPITX_DPHY_TXBYTEHS reset
>> +
>> +  reset-names:
>> +    items:
>> +      - const: dsi_txbytehs
>> +      - const: dphy_sys
>> +      - const: dphy_txbytehs
> 
> Drop 'dphy_'.
> 

OK, will drop "dphy_".

> Is 'dsi_txbytehs' really a part of the DPHY block? Sounds like it is 
> part of the DSI block. If so, the reset belongs there. If the phy driver 
> needs it, then it needs to go find the DSI block and get its reset.
> 

"dsi_txbytehs" is a reset of DSI block, it will be put back to DSI block and remove from DPHY block.

>> +
>> +  power-domains:
>> +    maxItems: 1
>> +
>> +  "#phy-cells":
>> +    const: 0
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - clock-names
>> +  - resets
>> +  - reset-names
>> +  - power-domains
>> +  - "#phy-cells"
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    phy@...e0000 {
>> +      compatible = "starfive,jh7110-dphy-tx";
>> +      reg = <0x295e0000 0x10000>;
>> +      clocks = <&voutcrg 14>;
>> +      clock-names = "dphy_txesc";
>> +      resets = <&syscrg 7>,
>> +               <&syscrg 10>,
>> +               <&syscrg 11>;
>> +      reset-names = "dsi_txbytehs", "dphy_sys", "dphy_txbytehs";
>> +      power-domains = <&aon_syscon 0>;
>> +      #phy-cells = <0>;
>> +    };
>> -- 
>> 2.17.1
>> 

thanks a lot.

Best Regards,
Shengyang