linux-kernel - Re: [RFC PATCH 0/5] RISC-V: Add dynamic TSO support

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Message-ID: <87plzzqp2r.fsf@mail.lhotse>
Date:   Sat, 25 Nov 2023 00:05:16 +1100
From:   Michael Ellerman <mpe@...erman.id.au>
To:     Peter Zijlstra <peterz@...radead.org>,
        Jonas Oberhauser <jonas.oberhauser@...weicloud.com>
Cc:     Christoph Muellner <christoph.muellner@...ll.eu>,
        linux-riscv@...ts.infradead.org, linux-kselftest@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Shuah Khan <shuah@...nel.org>,
        Jonathan Corbet <corbet@....net>,
        Anup Patel <apatel@...tanamicro.com>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        Andrew Jones <ajones@...tanamicro.com>,
        Guo Ren <guoren@...nel.org>,
        Daniel Henrique Barboza <dbarboza@...tanamicro.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Björn Töpel <bjorn@...osinc.com>,
        Alan Stern <stern@...land.harvard.edu>,
        Andrea Parri <parri.andrea@...il.com>,
        Will Deacon <will@...nel.org>,
        Daniel Lustig <dlustig@...dia.com>
Subject: Re: [RFC PATCH 0/5] RISC-V: Add dynamic TSO support

Peter Zijlstra <peterz@...radead.org> writes:
> On Fri, Nov 24, 2023 at 12:04:09PM +0100, Jonas Oberhauser wrote:
>
>> > I think ARM64 approached this problem by adding the
>> > load-acquire/store-release instructions and for TSO based code,
>> > translate into those (eg. x86 -> arm64 transpilers).
>> 
>> 
>> Although those instructions have a bit more ordering constraints.
>> 
>> I have heard rumors that the apple chips also have a register that can be
>> set at runtime.
>
> Oh, I thought they made do with the load-acquire/store-release thingies.
> But to be fair, I haven't been paying *that* much attention to the apple
> stuff.
>
> I did read about how they fudged some of the x86 flags thing.
>
>> And there are some IBM machines that have a setting, but not sure how it is
>> controlled.
>
> Cute, I'm assuming this is the Power series (s390 already being TSO)? I
> wasn't aware they had this.

Are you referring to Strong Access Ordering? That is a per-page
attribute, not a CPU mode, and was removed in ISA v3.1 anyway.

cheers