linux-kernel - Re: [PATCH] powerpc/85xx: Fix typo in code comment

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Message-ID: <4ce802db-b6d0-4eec-9ae2-5383a6f01843@csgroup.eu>
Date:   Fri, 24 Nov 2023 13:08:25 +0000
From:   Christophe Leroy <christophe.leroy@...roup.eu>
To:     Dario Binacchi <dario.binacchi@...rulasolutions.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     Kumar Gala <galak@...nel.crashing.org>,
        Michael Ellerman <mpe@...erman.id.au>,
        Nicholas Piggin <npiggin@...il.com>,
        Pali Rohár <pali@...nel.org>,
        Rob Herring <robh@...nel.org>, Scott Wood <oss@...error.net>,
        Timur Tabi <timur@...escale.com>,
        Zhicheng Fan <b32736@...escale.com>,
        "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Subject: Re: [PATCH] powerpc/85xx: Fix typo in code comment



Le 24/11/2023 à 11:02, Dario Binacchi a écrit :
> s/singals/signals/

Is that really worth it to spend time on such a change ?

By sending such a patch, you require people to spend time reviewing your 
patch, then maintainer has to spend time handling your patch.
Furthermore, as you added a Fixes: tag, LTS maintainers will have to 
spend time handling that too.

Do you really think that this typo is worth a patch ?

This kind of tiny error should be fixed through a more significant patch 
adressing this file. But it is not worth a patch on its own.

Christophe


> 
> Fixes: 04e358d896a7 ("powerpc/85xx: Add Quicc Engine support for p1025rdb")
> Signed-off-by: Dario Binacchi <dario.binacchi@...rulasolutions.com>
> ---
> 
>   arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> index ec9f60fbebc7..e0cec670d8db 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> @@ -76,7 +76,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
>   			/* P1025 has pins muxed for QE and other functions. To
>   			* enable QE UEC mode, we need to set bit QE0 for UCC1
>   			* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
> -			* and QE12 for QE MII management singals in PMUXCR
> +			* and QE12 for QE MII management signals in PMUXCR
>   			* register.
>   			*/
>   				setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |