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Message-ID: <20231129-thrower-umbilical-f11ee0749800@spud>
Date:   Wed, 29 Nov 2023 14:46:26 +0000
From:   Conor Dooley <conor@...nel.org>
To:     Sia Jee Heng <jeeheng.sia@...rfivetech.com>
Cc:     kernel@...il.dk, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, krzk@...nel.org,
        conor+dt@...nel.org, paul.walmsley@...ive.com, palmer@...belt.com,
        aou@...s.berkeley.edu, daniel.lezcano@...aro.org,
        tglx@...utronix.de, anup@...infault.org,
        gregkh@...uxfoundation.org, jirislaby@...nel.org,
        michal.simek@....com, michael.zhu@...rfivetech.com,
        drew@...gleboard.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        leyfoon.tan@...rfivetech.com
Subject: Re: [PATCH v2 2/6] dt-bindings: riscv: Add StarFive JH8100 SoC

On Wed, Nov 29, 2023 at 02:00:39PM +0800, Sia Jee Heng wrote:
> Add device tree bindings for the StarFive JH8100 RISC-V SoC.
> 
> Signed-off-by: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
> Reviewed-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com>

Acked-by: Conor Dooley <conor.dooley@...rochip.com>

Cheers,
Conor.

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