linux-kernel - Re: [PATCH v2 18/21] MIPS: mobileye: Add EyeQ5 dtsi

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Date:   Fri, 01 Dec 2023 11:56:22 +0100
From:   Gregory CLEMENT <gregory.clement@...tlin.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Paul Burton <paulburton@...nel.org>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        linux-mips@...r.kernel.org, Jiaxun Yang <jiaxun.yang@...goat.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:     Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
        Tawfik Bayouk <tawfik.bayouk@...ileye.com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Théo Lebrun <theo.lebrun@...tlin.com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v2 18/21] MIPS: mobileye: Add EyeQ5 dtsi

Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> writes:

> On 23/11/2023 16:26, Gregory CLEMENT wrote:
>> Add a device tree include file for the Mobileye EyeQ5 SoC.
>> 
>> Based on the work of Slava Samsonov <stanislav.samsonov@...el.com>
>> 
>> Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
>> ---
>
>
>> +	aliases {
>> +		serial0 = &uart0;
>> +		serial1 = &uart1;
>> +		serial2 = &uart2;
>> +	};
>> +
>> +	cpu_intc: interrupt-controller {
>> +		compatible = "mti,cpu-interrupt-controller";
>> +		interrupt-controller;
>> +		#address-cells = <0>;
>> +		#interrupt-cells = <1>;
>> +	};
>> +
>> +	gic: interrupt-controller@...000 {
>
> Why do you put MMIO nodes in top-level?

I can move it back under the soc node I think

>
>> +		compatible = "mti,gic";
>> +		reg = <0x0 0x140000 0x0 0x20000>;
>> +		interrupt-controller;
>> +		#interrupt-cells = <3>;
>> +
>> +		/*
>> +		* Declare the interrupt-parent even though the mti,gic
>> +		* binding doesn't require it, such that the kernel can
>> +		* figure out that cpu_intc is the root interrupt
>> +		* controller & should be probed first.
>> +		*/
>> +		interrupt-parent = <&cpu_intc>;
>> +
>> +		timer {
>> +			compatible = "mti,gic-timer";
>> +			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
>> +			clocks = <&core0_clk>;
>> +		};
>> +	};
>> +
>> +	soc: soc {
>
> Are you sure dtbs_check W=1 does not complain? I think you miss here
> address.

Yes dtbs_check W=1 does not complain. There is no reg property in this
node, so there is no address to add to the name of the node.

Gregory

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com