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Message-ID: <3e72bff6-9f4d-4cd4-845e-b065f1233ec6@collabora.com>
Date: Wed, 6 Dec 2023 11:59:54 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Daniel Golle <daniel@...rotopia.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Sabrina Dubroca <sd@...asysnail.net>,
Jianhui Zhao <zhaojh329@...il.com>,
Chen-Yu Tsai <wenst@...omium.org>,
"Garmin.Chang" <Garmin.Chang@...iatek.com>,
Sam Shih <sam.shih@...iatek.com>,
Frank Wunderlich <frank-w@...lic-files.de>,
Dan Carpenter <dan.carpenter@...aro.org>,
James Liao <jamesjj.liao@...iatek.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org
Subject: Re: [PATCH v3 2/4] dt-bindings: clock: mediatek: add clock
controllers of MT7988
Il 06/12/23 01:57, Daniel Golle ha scritto:
> Add various clock controllers found in the MT7988 SoC to existing
> bindings (if applicable) and add files for the new ethwarp, mcusys
> and xfi-pll clock controllers not previously present in any SoC.
>
> Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> ---
> v3:
> * move clock bindings to clock folder
> * drop ti,syscon-reset from bindings and example
> * merge mcusys with topckgen bindings
>
> v2:
> * dropped unused labels
> * add 'type: object' declaration for reset-controller found in new
> ethwarp controller and represented as ti,syscon-reset
> * rebase on top of
> "dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema"
>
> .../arm/mediatek/mediatek,infracfg.yaml | 1 +
> .../bindings/clock/mediatek,apmixedsys.yaml | 1 +
> .../bindings/clock/mediatek,ethsys.yaml | 1 +
> .../clock/mediatek,mt7988-ethwarp.yaml | 49 +++++++++++++++++++
> .../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++++++
> .../bindings/clock/mediatek,topckgen.yaml | 2 +
> .../bindings/net/pcs/mediatek,sgmiisys.yaml | 13 +++--
> 7 files changed, 112 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> index ea98043c6ba3d..230b5188a88db 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> @@ -30,6 +30,7 @@ properties:
> - mediatek,mt7629-infracfg
> - mediatek,mt7981-infracfg
> - mediatek,mt7986-infracfg
> + - mediatek,mt7988-infracfg
> - mediatek,mt8135-infracfg
> - mediatek,mt8167-infracfg
> - mediatek,mt8173-infracfg
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
> index 372c1d744bc27..685535846cbb7 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
> @@ -22,6 +22,7 @@ properties:
> - mediatek,mt7622-apmixedsys
> - mediatek,mt7981-apmixedsys
> - mediatek,mt7986-apmixedsys
> + - mediatek,mt7988-apmixedsys
> - mediatek,mt8135-apmixedsys
> - mediatek,mt8173-apmixedsys
> - mediatek,mt8516-apmixedsys
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
> index 94d42c8647777..f9cddacc2eae1 100644
> --- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
> +++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
> @@ -22,6 +22,7 @@ properties:
> - mediatek,mt7629-ethsys
> - mediatek,mt7981-ethsys
> - mediatek,mt7986-ethsys
> + - mediatek,mt7988-ethsys
> - const: syscon
> - items:
> - const: mediatek,mt7623-ethsys
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
> new file mode 100644
> index 0000000000000..9b919a155eb13
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7988-ethwarp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT7988 ethwarp Controller
> +
> +maintainers:
> + - Daniel Golle <daniel@...rotopia.org>
> +
> +description:
> + The Mediatek MT7988 ethwarp controller provides clocks and resets for the
> + Ethernet related subsystems found the MT7988 SoC.
> + The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
> +
> +properties:
> + compatible:
> + items:
> + - const: mediatek,mt7988-ethwarp
> + - const: syscon
> + - const: simple-mfd
No, this is not a mfd, I say.
Prove me wrong! :-)
..snip..
> diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
> index 66a95191bd776..68632cda334bd 100644
> --- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
> +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
> @@ -15,15 +15,22 @@ description:
>
> properties:
> compatible:
> - items:
> - - enum:
> + oneOf:
> + - items:
> + - enum:
> - mediatek,mt7622-sgmiisys
> - mediatek,mt7629-sgmiisys
> - mediatek,mt7981-sgmiisys_0
> - mediatek,mt7981-sgmiisys_1
> - mediatek,mt7986-sgmiisys_0
> - mediatek,mt7986-sgmiisys_1
> - - const: syscon
> + - const: syscon
> + - items:
> + - enum:
> + - mediatek,mt7988-sgmiisys_0
> + - mediatek,mt7988-sgmiisys_1
> + - const: syscon
> + - const: simple-mfd
Same.
Cheers,
Angelo
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